W90221X Winbond Electronics Corp America, W90221X Datasheet - Page 19

• Manufacturer Part Number: W90221X
• Description: Pa-risc Embedded Controller
• Manufacturer: Winbond Electronics Corp America

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5.4 PA-RISC CPU core
5.4.1 Features
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5.4.2 Related Pins
PWRON (input)
INTR0 (input)
INTR1 (input)
W90221X version 0.6
Test Mode (PLL is disable)
Base on PA-RISC 1.1 level-0 architecture
32-bit integer instruction set and register files
Maximum 100 MHz operation frequency
3.3V and 0.01W/MHz at full speed operation
High-speed 32-bit integer pipeline design
On-chip cache memory
Dynamic branch prediction
One high speed (2 CPU cycles) 16-/32-bit MAC and multimedia extended instructions
have been built-in for DSP related calculation
Specific serial-ICE-interface to facilitate chip debugging and software development
System Power-On Reset signal; Set this signal to logic high will reset the chip and force
all megacells returned to their initial states.
This pin serves as an "external interrupt request". Set this signal to logic 1 will also set
EIER[12] to logic 1. (The 16-bit IDE slot can use this pin as its interrupt request).
6 stages for Load/Store instructions
5 stages for other instructions
4 KB, direct-map instruction cache and 4 KB, 4-way set-associative data cache
One level read buffer and wrap-around support in each cache
One level write buffer and hit-under-miss support in data cache
Cache-locking support in instruction cache
Build-in 1-level 256 entry, 4-way set-associative (LRU) Branch-Target-Buffer to
improve branch prediction rate and accelerate pipeline throughput
EXTCLK = CPUCLK/3, CPUCLK/4, CPUCLK/5, CPUCLK/6
MCLK = CPUCLK/1, CPUCLK/1.5, CPUCLK/2
OSC = DPCLK/2 = 13.5MHz
DPCLK = 27MHz
VCLK = 27MHz
GFXCLK = 66MHz
PCLK = DPCLK/2 = 13.5MHz
CPUCLK = GFXCLK = 66MHz (for instance)
EXTCLK = CPUCLK / 2 = 33MHz
MCLK = CPUCLK = 66MHz
OSC = CPUCLK / 4 = 16.5MHz
Write-through and write-back support for data cache
= GFXCLK/2 = 18.432MHz
(MD[24] = 0 on power-on reset)
(MD[24] = 1 on power-on reset)
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