W90221X Winbond Electronics Corp America, W90221X Datasheet - Page 31

• Manufacturer Part Number: W90221X
• Description: Pa-risc Embedded Controller
• Manufacturer: Winbond Electronics Corp America

REQ1# (In)
SERR# (In)
INTA# (In)
INTB# (In)
INTC# (In)
PCIRST# (output)
GNT0# (output)
GNT1# (output)
GPIO[16:15] (output)
5.9.4 Operation Modes
DX3 Mode
DX4 Mode
DX5 Mode
DX6 Mode
PCICLK skew control
W90221X version 0.6
Each PCI master has a pair of arbitration lines that connect it directly to the W902321X.
When a master requires the use of the PCI bus, it REQ0# is the PCI bus request signal
used as an input to indicate the arbiter that the master requires the use of the PCI bus.
REQ1# is the PCI bus request signal used as an input to indicate the arbiter that this
master 1 desires use of the bus.
SERR# is the system error reporting, if SERR# asserted and Master 0 Latency Register
bit16 =1, it will generate a NMI (non-maskable interrupt).
PCI agent can utilize the PCI Interrupt request line A, INTA#, to generate request for
service.
PCI agent can utilize the PCI Interrupt request line B, INTB#, to generate request for
service.
PCI agent can utilize the PCI Interrupt request line C, INTC#, to generate request for
service.
PCIRST# is used to reset PCI device.
GNT0# is the PCI bus grant output signals generated by the internal PCI arbiter.
GNT1# is the PCI bus grant output signals generated by the internal PCI arbiter.
If ECP not enable, the GPIO[16:15] indicates PCI bus grant output GNT[3:2]#.
Once MD[26:27] is set to 00 during power on reset, the PCICLK will operate at
CPUCLK/3 frequency.
Once MD[26:27] is set to 01during power on reset, the PCICLK will operate at
CPUCLK/4 frequency.
Once MD[26:27] is set to 10 during power on reset, the PCICLK will operate at
CPUCLK/5 frequency.
Once MD[26:27] is set to 11 during power on reset, the PCICLK will operate at
CPUCLK/6 frequency.
Bit 17 ~ 20 of "Master 2 Latency Register" are used to adjust the skew of PCICLK so as
to make all other PCI control signals get enough setup and hold time relative to PCICLK.
Some typical value are suggested as follows:
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