SPC7281 Epson Electronics America, Inc., SPC7281 Datasheet - Page 33

• Manufacturer Part Number: SPC7281
• Description: IEEE1394 Controller
• Manufacturer: Epson Electronics America, Inc.

Address Register Name
0x1C
0x1D
0x1A
0x1B
0x1E
0x1F
0x18
0x19
LinkCtl_H
LinkCtl_L
LinkStat
PriReqCnt
RetryLimit_H
RetryLimit_L
MaxRetry
IRM_Stat
7: PassSelfID
6: PassPhyPkt
5: PassBrPkt
4: EnPosWB
3: EnPosWQ
2: APHY
1: EnAcc
0: Cmstr
7: EnLink
6:
5: PLIFrst
4: IgnrBChdr
3: IgnrBCdata
2: RxBusyMode
1: DualRtyEnb
0: SinglRtyEnb
7:
6:
5:
4:
3:
2: ID_Valid
1: Root
0: CablPwSts
7:
6:
5: PriReq[5]
4: PriReq[4]
3: PriReq[3]
2: PriReq[2]
1: PriReq[1]
0: PriReq[0]
7: SecLimit[2]
6: SecLimit[1]
5: SecLimit[0]
4: CycLimt[12]
3: CycLimt[11]
2: CycLimt[10]
1: CycLimt[9]
0: CycLimt[8]
7: CycLimt[7]
6: CycLimt[6]
5: CycLimt[5]
4: CycLimt[4]
3: CycLimt[3]
2: CycLimt[2]
1: CycLimt[1]
0: CycLimt[0]
7:
6:
5:
4:
3: maxRty[3]
2: maxRty[2]
1: maxRty[1]
0: maxRty[0]
7: NoIRM
6: WonIRM
5: IRMID[5]
4: IRMID[4]
3: IRMID[3]
2: IRMID[2]
1: IRMID[1]
0: IRMID[0]
Bit Symbol
R(W)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
R
R
R
R
R
0: Non PassSelfID
0: Non Pass PHY Packet
0: Non Pass BusRst Packet
0: Disable Posted WB
0: Disable Poosted WQ
0: PHY 1394.a uncorrespond 1: PHY 1394.a correspond
0: Ack Acceleration Disable
0: Cycle Master Not Capabl
0: Disable Link
0:
0: NONE
0: BC Pkt to DMA FIFO
0: BC Data to DMA FIFO
0: Dual
0: Dual Retry Disable
0: Single Retry Disable
0:
0:
0:
0:
0:
0: PhyID Invalid
0: Self Node = Not Root
0: Cable Power Status NG
0:
0:
Maximum Number of certain Priority Arb Request
Dual Phase Retry Limit
Second Limit
Cycle Limit
If (SecLimit == 0 and CycLimit==0)
Dual Phase is ignore
0:
0:
0:
0:
Single Phase Retry Limit
Max Retry Count Value
If maxRty == 0, Single Phase Retry is ignore
0: Exist IRM Node
0: Other Node
Physical ID of IRM Node
No exist IRM Node then IRMID= 0x3F
EPSON
Description
1: Self–ID to DMA FIFO
1: PHY Pkt to DMA FIFO
1: BusRst Pkt to DMA FIFO
1: Enable Posted WB
1: Enable Posted WQ
1: Ack Acceleration Enable
1: Cycle Master Capable
1: Enable Link
1:
1: Reset PHY/Link I/F
1: Ignore BC Packet
1: Ignore BC–Data
1: Single
1: Dual Retry Enable
1: Single Retry Enable
1:
1:
1:
1:
1:
1: PhyID Valid
1: Self Node = Root
1: Cable Power Status OK
1:
1:
1:
1:
1:
1:
1: None IRM Node
1: Self Node
H.Rst
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x3F
S1R72801F00A
S.Rst
0x00
0x00
0x00
0x00
0x00
–
0
0
0
0
0
0
–
–
B.Rst
0x3F
0x00
–
–
–
–
–
–
–
–
–
–
–
–
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