SPC7281 Epson Electronics America, Inc., SPC7281 Datasheet - Page 46

• Manufacturer Part Number: SPC7281
• Description: IEEE1394 Controller
• Manufacturer: Epson Electronics America, Inc.

S1R72801F00A
8.1.4 Detail Description of Register
(The base address of this register is 0x100000.)
Main Interrupt Status Register
Note) The bits of this register control the XInt of output pin. Writing to this register negates the XInt once even if the
Bit7 Sub Interrupt Status
Bit 6 Isochronous Packet Transmit Complete
Bit5 Receive Packet DMA Complete
Bit4 Asynchronous Packet Transmit Complete
Bit 3 HwSBP2 Process Complete
Bit2 IDE DMA Transmit Complete
Bit1 IDE Interface Interrupt
Bit0 BusReset Detected
42
Address Register Name
0x00
When this IC interrupts the CPU, the CPU first reads this register to handle it, indicating which Interrupt Status
Register is a factor of this interrupt.
Subsequent to reading this register, the SubIntStat (Bit 7) reads an Interrupt Status Register associated with each
bit to confirm which bit is an interrupt source and appropriately handle it. After that, it writes the read value
to the Interrupt Status Register to clear the bit. In the case the interrupt factor still remains, however, the bit is
not cleared.
When one of 7 bits of the TxIsoCmp, RxDmaCmp, TxAsyCmp, HwSBP2Cmp, IDE_DmaCmp, IDE_INTRQ,
and BusReset other than above is an interrupt source, this register clears the bit by writing the read value.
interrupt factor remains, asserting the XInt after a certain period. (Ready for a timer or edge interrupt).
When an interrupt factor exists at each bit shown at the SubIntStat Register, this bit becomes “1”.
When an ISO Packet Transmit is complete, this bit becomes “1”.
When a received packet is written to the Receive Buffer Area, this bit becomes “1”.
When an Ack packet to an Async Transmit packet is received, this bit becomes “1”.
The Ack code is written to the footer area of the Transmit Packet Header.
When a HwSBP2 processing is complete, this bit becomes “1”.
When an IDE I/F DMA Transmit is complete, this bit becomes “1”.
When the INTRQ signal is asserted to the IDE I/F, this bit becomes “1”.
When a BusReset signal is detected on the 1394 Serial Bus, this bit becomes “1”.
When it issues a BusReset, this bit becomes “1” as well.
MainIntStat
7:SubIntStat
6: TxIsoCmp
5: RxDmaCmp
4: TxAsyCmp
3: HwSBP2Cmp R(W) 0: None
2: IDE_DmaCmp R(W) 0: None
1: IDE_INTRQ
0: BusReset
Bit Symbol
R(W) 0: None
R(W) 0: None
R(W) 0: None
R(W) 0: None
R(W) 0: None
R(W) 0: None
R/W
EPSON
1: Sub Interrupt Occurred
1: ISO Pkt Transmit Done
1: Packet Reception
1: AckCode Reception
1: HwSBP2 Process Complete
1: IDE DMA Transmit Complete
1: IDE Interface Interrupt
1: Bas Reset Detected
Description
H.Rst S.Rst B.Rst
0x00 0x00
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