SPC7281 Epson Electronics America, Inc., SPC7281 Datasheet - Page 56

• Manufacturer Part Number: SPC7281
• Description: IEEE1394 Controller
• Manufacturer: Epson Electronics America, Inc.

S1R72801F00A
LINK Core Control Register Lower Rank
Bit7 Enable LINK
Bit6 Reserved
Bit5 PHY/LINK Interface Reset
Bit4 Ignore Broadcast Packet
Bit3 Ignore Broadcast Packet Data
Bit2 Rx Busy Mode
Bit1 Dual Phase Retry Enable
Bit0 Single Phase Retry Enable
Link Core Status Read Register
Bit 7..3 Reserved
Bit2 ID_Valid
Bit1 Root
Bit 0 Cable Power Status
52
Address Register Name
Address Register Name Bit Symbol R/W
0x19
0x1A
This register controls the functions of the LINK core.
Controls whether communications with other nodes are enabled.
When this bit is “0”, no response is given to a received packet. When it is “1”, the transmission/reception of
a packet becomes possible. Even if you set the EnLINK to “1” when the LPS bit is “0”, it is ignored. Before
setting it to “1”, set the LPS bit to “1” and wait 10ms.
Writing “1” to this bit resets the PHY/LINK interface. After resetting it, this bit is automatically restored to “0”.
Setting this bit to “1” abandons a Broadcast packet received by the LINK core.
Setting this bit to “1” abandons a Broadcast data received by he LINK core.
Sets a Busy type, the Dual Phase mode or Single Phase mode, for a received packet when returning a Busy.
When this is “1”, an ack_busy_X is returned. When it is “0”, an ack_busy_A or ack_busy_B is returned.
Controls whether the Dual Phase retry protocol is enabled.
When this bit is “1”, a retry processing is done until a time set on the Retry Limit Register is exceeded. When
it is “0”, no retry is done. When the value of the Retry Limit Register is “0”, a retry processing is ignored.
Controls whether the Single Phase retry protocol is enabled.
When this bit is “1”, a retry processing is done until the number set on the Retry Limit Register is exceeded.
When it is “0”, a retry processing is disabled. When the value of the MaxRetry Register is “0”, a retry processing
is ignored.
When this bit is set to “1,” the Physical_ID of the NodeID register becomes valid, and when this bit is set to “0,”
the Physical_ID becomes invalid.
This bit is set to “1” when the self node comes to Root in the Self-ID process after the bus is reset.
This bit indicates the status of Cable Power, which is updated in the PHY Status.
“1” : Cable Power Status OK
“0” : Cable Power Status NG
LinkCtl_L
LinkStart
7:
6:
5:
4:
3:
2: ID_Valid
1: Root
0: CablPwSts
7: EnLink
6:
5: PLIFrst
4: IgnrBChdr
3: IgnrBCdata
2: RxBusyMode
1: DualRtyEnb
0: SinglRtyEnb
Bit Symbol
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0:
0:
0:
0:
0:
0: PhyID Invalid
0: Self Node =Not Root
0: Cable Power Status NG 1: Cable Power Status OK
W
EPSON
0: Disable Link
0:
0: None
0: BC Pkt to DMA FIFO 1: Ignore BC Packet 0x00
0: BC Data to DMA FIFO 1: Ignore BC – Data
0: Dual
0: Dual Retry Disable 1: Dual Retry Enable
0: Single Retry Disable 1: Single Retry Enable
Description
Description
1:
1:
1:
1:
1:
1: PhyID Valid
1: Self Node =Root
1: Enable Link
1:
1: Reset PHY/Link I/F
1: Single
H.Rst S.Rst B.Rst
H.Rst S.Rst B.Rst
0x00
–
–
0
0
0
0
0
0
–
–
–
–
–
–
–
–
–
–