SPC7281 Epson Electronics America, Inc., SPC7281 Datasheet - Page 48

• Manufacturer Part Number: SPC7281
• Description: IEEE1394 Controller
• Manufacturer: Epson Electronics America, Inc.

S1R72801F00A
DMA Interrupt Status Register
Bit7 Reserved
Bit6 Transmit Async Packet Retry Go
Bit5 Transmit Async Broadcast Packet Sent
Bit4 Receive Packet LINK DMA Failed
Bit3 Transmit Async Packet LINKDMA Failed
Bit2 Transmit ISO Packet LINKDMA Failed
Bit 1 Transmit Async Packet BusReset Abort
Bit0 Transmit Async Packet Ack-code Missing
44
Address Register Name
0x03
The value of each bit of this register indicates the status of a corresponding interrupt source. If these bits become
“H” when the associated bit of the DMAIntEnb Register is “1”, this register asserts the interrupt signal to the
CPU.
The CPU reads this register after receiving the interrupt signal to locate an interrupt source. By writing the read
value again, it clears these bits.
When a Sub Action Gap is detected in PHY status of PHY/LINK interface, this bit becomes “1”.
When an auto retry is performed after transmitting an Async packet and receiving an Ack_busy, this bit becomes
“1”.
After a transmission of a Broadcast packet of Async or a PHY packet finishes, this bit becomes “1”.
When a received packet cannot be written to the buffer due to the following reasons, this bit becomes “1”.
1) DMA was too late.
2) A packet was received when the ForceBusy bit is on.
When data cannot be transferred from the buffer to the LINK core at the time of Async packet transmission
(DMA FIFO is Under Flow), this bit becomes “1”.
When data cannot be transferred from the buffer to the LINK core at the time of ISO packet transmission (DMA
FIFO is Under Flow), this bit becomes “1”.
When a Transmit packet is disabled by a BusReset before an Ack packet is returned at the time of Async packet
transmission, this bit becomes “1”.
When a Ack packet is not returned at the time of Async packet transmission, this bit becomes “1”.
DmaIntStat
7:
6: TxAsyRtyGo
5: TxAsyBCSent R(W) 0: None
4: RxDmaFaild
3: TxAsyFaild
2: TxIsoFaild
1: TxAsyBRAbort R(W) 0: None
0: TxAsyMiss
Bit Symbol
R(W) 0: None
R(W) 0: None
R(W) 0: None
R(W) 0: None
R(W) 0: None
R/W
EPSON
0:
1:
1: Async Tx Retry Go
1: AsyncTxBroadcast Sent
1: Rx DMA Failed
1: Async Tx Failed
1: ISO Tx Failed
1: Async Tx BusReset Abort
1: AsyncTxAckCodeMissing
Description
H.Rst S.Rst B.Rst
0x00 0x00
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