MC145151 Motorola, MC145151 Datasheet - Page 18

• Manufacturer Part Number: MC145151
• Description: Parallel-Input PLL Frequency Synthesizer
• Manufacturer: Motorola

INPUT PINS
f in
Frequency Input (Pin 8)
this input decrements the
inverter biased in the linear region to allow use with ac
coupled signals as low as 500 mV p–p. For larger amplitude
signals (standard CMOS logic levels), dc coupling may be
used.
CLK, DATA
Shift Clock, Serial Data Inputs (Pins 9, 10)
data into the on–chip shift registers. The last data bit entered
determines which counter storage latch is activated; a logic 1
selects the reference counter latch and a logic 0 selects the
ENB
Latch Enable Input (Pin 11)
ter into the reference divider or N latches depending on the
control bit. The reference divider latches are activated if the
control bit is at a logic high and the
MC145151–2 through MC145158–2
18
N counter latch. The entry format is as follows:
Input frequency from VCO output. A rising edge signal on
Each low–to–high transition of the clock shifts one bit of
A logic high on this pin latches the data from the shift regis-
OSC out
REF out
OSC in
DATA
ENB
CLK
f in
PIN DESCRIPTIONS
CONTROL
FIRST DATA BIT INTO SHIFT REGISTER
1–BIT
S/R
N counter. This input has an
N latches are activated
MC145157–2 BLOCK DIAGRAM
REFERENCE COUNTER LATCH
14–BIT SHIFT REGISTER
14–BIT SHIFT REGISTER
14–BIT
14–BIT
if the control bit is at a logic low. A logic low on this pin allows
the user to change the data in the shift registers without
affecting the counters. ENB is normally low and is pulsed
high to transfer data to the latches.
OSC in , OSC out
Reference Oscillator Input/Output (Pins 1, 2)
nected to terminals of an external parallel resonant crystal.
Frequency setting capacitors of appropriate value must be
connected from OSC in to ground and OSC out to ground.
OSC in may also serve as the input for an externally–gener-
ated reference signal. This signal is typically ac coupled to
OSC in , but for larger amplitude signals (standard CMOS
logic levels) dc coupling may also be used. In the external
reference mode, no connection is required to OSC out .
OUTPUT PINS
PD out
Single–Ended Phase Detector A Output (Pin 5)
produces a loop–error signal that is used with a loop filter to
control a VCO.
Double–Ended Phase Detector B Outputs (Pins 16, 15)
signal. A single–ended output is also available for this pur-
pose (see PD out ).
N COUNTER LATCH
R , V
These pins form an on–chip reference oscillator when con-
This single–ended (three–state) phase detector output
Frequency f V > f R or f V Leading: Negative Pulses
Frequency f V < f R or f V Lagging: Positive Pulses
Frequency f V = f R and Phase Coincidence: High–Imped-
These outputs can be combined externally for a loop–error
ance State
R COUNTER
N COUNTER
14
14
14
14
DETECTOR
DETECTOR
DETECT
PHASE
PHASE
LOCK
A
B
MOTOROLA
f R
LD
PD out
f V
S/R out
V
R