74F1071 Fairchild Semiconductor, 74F1071 Datasheet

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... Undershoot/Overshoot Clamp and ESD Protection Device General Description The 74F1071 is an 18-bit undershoot/overshoot clamp which is designed to limit bus voltages and also to protect more sensitive devices from electrical overstress due to electrostatic discharge (ESD). The inputs of the device aggressively clamp voltage excursions nominally at 0.5V below and 7V above ground ...

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Absolute Maximum Ratings Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias Input Voltage (Note 2) Input Current (Note 2) 200 ESD (Note 3) Human Body Model (MIL-STD-883D method 3015.7) IEC 801-2 Machine Model (EIAJIC-121-1981) ...

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DC Electrical Characteristics Typical Reverse Conduction Characteristics ESD Network CZ Human Body Model 100 pF IEC 801-2 150 pF Typical Forward and Reverse V/I Characteristics Typical Forward Conduction Characteristics RZ 1500 Simulated ESD Voltage Clamping Test Circuit 330 3 www.fairchildsemi.com ...

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... DC Electrical Characteristics Unclamped + 1 KV ESD Voltage Waveform (IEC801-2 Network) Unclamped - 1 KV ESD Voltage Waveform (IEC801-2 Network) Typical Application 74F1071 ESD Protection of ASIC on User Port www.fairchildsemi.com (Continued) Clamped + 1 KV ESD Voltage Waveform (IEC801-2 Network) Clamped - 1 KV ESD Voltage Waveform (IEC801-2 Network) 4 ...

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Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide Package Number M20B Package Number MSA20 5 www.fairchildsemi.com ...

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Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves ...