IDT70V07 Integrated Device Technology, IDT70V07 Datasheet - Page 12

• Manufacturer Part Number: IDT70V07
• Description: 32k X 8 3.3v Dual-port
• Manufacturer: Integrated Device Technology

Timing Waveform of Write with BUSY
NOTES:
1. t
2. BUSY is asserted on Port "B" blocking R/W
Waveform of BUSY Arbitration Controlled by CE Timing
Waveform of BUSY Arbitration Cycle Controlled by Address Match Timing
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from Port “A”.
2. If t
IDT70V07S/L
High-Speed 32K x 8 Dual-Port Static RAM
ADDR
ADDR
BUSY
WH
ADDR
BUSY
APS
must be met for both BUSY input (SLAVE) and output (MASTER).
and
CE
CE
is not satisfied, the BUSY signal will be asserted on one side or the other, but there is no guarantee on which side busy will be asserted.
"A"
"B"
"B"
"A"
"B"
"A"
"B"
"B"
t
BUSY
APS
R/W
R/W
(2)
"A"
"B"
"B"
"B"
t
APS
, until BUSY
(2)
t
BAA
MATCHING ADDRESS "N"
"B"
ADDRESS "N"
goes HIGH.
t
WB
t
BAC
ADDRESSES MATCH
12
t
WP
(2)
Industrial and Commercial Temperature Ranges
t
t
BDA
BDC
t
WH
(1)
2943 drw 14
(1)
2943 drw 15
2943 drw 16
(1)