IDT70V07 Integrated Device Technology, IDT70V07 Datasheet - Page 9

• Manufacturer Part Number: IDT70V07
• Description: 32k X 8 3.3v Dual-port
• Manufacturer: Integrated Device Technology

Timing Waveform of Write Cycle No. 1, R/W Controlled Timing
Timing Waveform of Write Cycle No. 2, CE Controlled Timing
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (t
3. t
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last, CE or R/W.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load
8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of t
9. To access SRAM, CE = V
CE or SEM
CE or SEM
ADDRESS
ADDRESS
IDT70V07S/L
High-Speed 32K x 8 Dual-Port Static RAM
DATA
(Figure 2).
bus for the required t
WR
DATA
DATA
is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.
R/W
OUT
R/W
OE
IN
IN
(9)
(9)
DW
. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t
IL
and SEM = V
t
AS
EW
t
AS
t
(6)
LZ
or t
(6)
IH
WP
. To access semaphore, CE = V
) of a LOW CE and a LOW R/W for memory array writing cycle.
(4)
t
WZ
t
(7)
AW
t
t
WC
AW
t
WC
t
WP
t
EW
(2)
IH
(2)
and SEM = V
9
t
DW
WP
IL
t
DW
. t
or (t
EW
WZ
must be met for either condition.
+ t
t
DH
DW
t
t
OW
WR
Industrial and Commercial Temperature Ranges
) to allow the I/O drivers to turn off and data to be placed on the
(3)
t
WR
t
DH
(3)
t
(4)
HZ
t
(7)
HZ
(1,5)
(1,5,8)
(7)
2943 drw 09
2943 drw 10
WP
.
,