HT49CV5 Holtek Semiconductor, HT49CV5 Datasheet - Page 14

• Manufacturer Part Number: HT49CV5
• Description: A/D
• Manufacturer: Holtek Semiconductor

Watchdog Timer - WDT
The WDT clock source is implemented by a dedicated
RC oscillator (WDT oscillator) or an instruction clock
(system clock/4) or a real time clock oscillator (RTC os-
cillator). The timer is designed to prevent a software
malfunction or sequence from jumping to an unknown
location with unpredictable results. The WDT can be
disabled by options. But if the WDT is disabled, all exe-
cutions related to the WDT lead to no operation.
Once an internal WDT oscillator (RC oscillator with a pe-
riod of 65 s at 5V) is selected, it is divided by 2
(by configuration option to get the WDT time-out period).
The minimum WDT time-out period is 300ms~600ms.
This time-out period may vary with temperature, VDD
and process variations. By selecting the WDT configura-
tion option, longer time-out periods can be realized. If
the WDT time-out is selected, 2
time-out period is divided by 2
If the WDT oscillator is disabled, the WDT clock may still
come from the instruction clock and operates in the
same manner except that in the halt state the WDT may
stop counting and lose its protecting purposes. In this
situation the logic can only be restarted by external
logic. If the device operates in a noisy environment, us-
ing the on-chip RC oscillator (WDT OSC) is strongly rec-
ommended since the HALT will stop the system clock.
The WDT overflow under normal operation initializes a
mode, the overflow initializes a warm reset , and only
the Program Counter and SP are reset to zero. To clear
the contents of the WDT, there are three methods to be
adopted, i.e., external reset (a low level to RES), soft-
ware instruction, and a HALT instruction. There are
two types of software instructions; CLR WDT and the
other set
two types of instruction, only one type of instruction can
be active at a time depending on the options
WDT times selection option. If the CLR WDT is se-
lected (i.e., CLR WDT times is equal to one), any execu-
tion of the CLR WDT instruction clears the WDT. In the
case where the two CLR WDT1 and CLR WDT2 in-
structions are chosen (i.e., CLR WDT times is equal to
two), these two instructions have to be executed to clear
the WDT, otherwise, the WDT may reset the chip due to
time-out.
Rev. 1.20
chip reset and sets the status bit TO . In the HALT
CLR WDT1 and CLR WDT2 . Of these
15
~2
16
which is 2.3s~4.7s.
15
, the maximum
12
Watchdog Timer
~2
CLR
15
14
Multi-function Timer
The HT49RV5/HT49CV5 provides a multi-function timer
for the and RTC but with different time-out periods. The
multi-function timer consists of an 8-stage divider and a
7-bit prescaler, with the clock source coming from the
RTC OSC or the instruction clock (i.e., system clock di-
vided by 4). The multi-function timer also provides a
selectable frequency signal (ranging from f
for the VFD driver circuits, and a selectable frequency
signal (ranging from f
by options. It is recommended to select a frequency as
close as possible to 32kHz for the VFD driver circuits to
obtain good display clarity.
Real Time Clock - RTC
The real time clock (RTC) is used to supply a regular in-
ternal interrupt. Its time-out period ranges from f
f
RT1 and RT0 (bits 2, 1, 0 of RTCC; 09H) yields various
time-out periods. If the RTC time-out occurs and the in-
terrupt is enabled, the related interrupt request flag
(RTF; bit 1 of MFIS) is set and the multi-function inter-
rupt request flag (MFF; bit 6 of INTC1) is set. If the inter-
rupt (EMFI) is enabled, and the stack is not full, a
subroutine call to location 18H occurs.
Note: * not recommended to be used
S
/2
RT2
15
0
0
0
0
1
1
1
1
by software programming. Writing data to RT2,
RT1
0
0
1
1
0
0
1
1
RT0
0
1
0
1
0
1
0
1
S
/2
HT49RV5/HT49CV5
1
to f
RTC Clock Divided Factor
S
/2
8
) for the buzzer output
2
2
2
2
2
2
2
2
10
11
12
13
14
15
8
9
*
*
*
*
April 14, 2006
S
/2
0
to f
S
/2
S
8
/2
to
7
)