HT49CV5 Holtek Semiconductor, HT49CV5 Datasheet - Page 23

• Manufacturer Part Number: HT49CV5
• Description: A/D
• Manufacturer: Holtek Semiconductor

Input/Output Ports
There are 20 bidirectional input/output lines in the
microcontroller, labeled as PA, PB, PC and PD, which
are mapped to the data memory of [12H], [14H], [16H]
and [18H], respectively. All of these I/O ports can be
used for input and output operations. For input opera-
tion, these ports are non-latching, that is, the inputs
must be ready at the T2 rising edge of instruction ²MOV
A,[m]² (m=12H, 14H, 16H or 18H). For output operation,
all the data is latched and remains unchanged until the
output latch is rewritten.
Each I/O line has its own control register (PAC, PBC,
PCC, PDC) to control the input/output configuration.
With this control register, CMOS output or Schmitt Trig-
ger input with or without pull-high resistor structures can
be reconfigured dynamically under software control. To
function as an input, the corresponding latch of the con-
trol register must write a ²1². The input source also de-
pends on the control register. If the control register bit is
²1², the input will read the pad state. If the control regis-
ter bit is ²0², the contents of the latches will move to the
in te rn a l b us . Th e l atter i s pos si bl e in the
²read-modify-write² instruction.
For an output function, CMOS is the only configuration.
These control registers are mapped to locations 13H,
15H, 17H and 19H.
After a chip reset, these input/output lines remain at high
levels or floating state (depending on pull-high options).
Each bit of these input/output latches can be set or
cleared by ²SET [m].i² and ²CLR [m].i² (m=12H, 14H,
16H or 18H) instructions.
Rev. 1.20
¨
Slave mode operation
Step1: CKS don¢t care and select M1, M0 =11
Step2: Select CSEN, MLS (the same as the master)
Step3: Set SBEN
Step4: Writing data to SBDR
-
-
-
Step5: Check WCOL
-
-
Step6: Check TRFor waiting for serial bus interrupt
Step7: Read data from SBDR
Step8: Clear TRF
Step9: Go to step 4
Note: SIO internal operation:
data is stored in the TXRX buffer
waiting for master clock signal (and SCS): SCK
go to step 5
WCOL=1, clear WCOL, go to step 4
WCOL=0, go to step 6
* SCK (SCS) received
* output data in TXRX buffer and SDI data
* data transferred, data in TXRX buffer is
is shifted into TXRX buffer
latched into SBDR
23
Some instructions first input data and then follow the
output operations. For example, ²SET [m].i², ²CLR
[m].i², ²CPL [m]², ²CPLA [m]² read the entire port states
into the CPU, execute the defined operations
(bit-operation), and then write the results back to the
latches or the accumulator.
Each line of port A has the capability of waking-up the
device.
Each I/O port has a pull-high option. Once the pull-high
option is selected, the I/O port has a pull-high resistor,
otherwise, there¢s none. Take note that a non-pull-high
I/O port operating in input mode will cause a floating
state.
The PA3 pin is pin-shared with the PFD signal. If the
PFD option is selected, the output signal in the output
mode of PA3 will be the PFD signal generated by the
timer/event counter overflow signal. The input mode al-
ways retains its original functions. Once the PFD option
is selected, the PFD output signal is controlled by the
PA3 data register only. Writing a ²1² to PA3 data register
will enable the PFD output function and writing a ²0² will
force the PA3 pin to remain at ²0². The I/O functions of
PA3 are shown below.
Note:
The descriptions of PFD control signal and PFD output
frequency are listed in the following table.
Note:
The PA0 and PA1 pins are pin-shared with the BZ and
BZ signal, respectively. If the BZ/BZ option is selected,
the output signal in the output mode of PA0/PA1 will be
the buzzer signal generated by the multi-function timer.
The input mode always remains in its original function.
Once the BZ/BZ option is selected, the buzzer output
signal are controlled by the PA0/PA1 data register only.
Mode
Timer
PA3
OFF
OFF
ON
ON
I/O
The PFD frequency is the timer/event counter
overflow frequency divided by 2.
²X² stands for unused
²U² stands for unknown
²M² is ²65536² for PFD0 or PFD1
²N² is preload value for timer/event counter
²f
counter
Preload
(Normal)
Timer
Value
TMR
Logical
Input
X
X
N
N
I/P
² is input clock frequency for timer/event
PA3 Data
Register
(Normal)
Logical
Output
0
1
0
1
O/P
HT49RV5/HT49CV5
PA3 Pad
State
PFD
U
0
0
Logical
(PFD)
Input
I/P
f
TMR
Frequency
April 14, 2006
(Timer on)
/[2´(M-N)]
PFD
(PFD)
X
X
X
PFD
O/P