HT49CV5 Holtek Semiconductor, HT49CV5 Datasheet - Page 31

• Manufacturer Part Number: HT49CV5
• Description: A/D
• Manufacturer: Holtek Semiconductor

Application Circuits
Note:
Rev. 1.20
LVR selection
LVR has enable or disable options
PFD selection. If PA3 is set as a PFD output, there are two types of selections; One is PFD0 as the PFD output, the
other is PFD1 as the PFD output. PFD0, PFD1 are the timer overflow signals of the Timer/Event Counter 0,
Timer/Event Counter 1, respectively.
PWM selection: (7+1) or (6+2) mode
PD0: level output or PWM0 output
PD1: level output or PWM1 output
INT0 or INT1 triggering edge: Disable; high to low; low to high; low to high or high to low
SIOCLK: Serial interface clock. There are falling edge, rising edge or triggering edge
CSEN: Serial bus selection: enable or disable
WCOL: SBDR write conflict
The resistance and capacitance for reset circuit should be designed in such a way as to ensure that the VDD is
stable and remains within a valid operating voltage range before bringing RES to high.
Options
31
HT49RV5/HT49CV5
April 14, 2006