HT49CV5 Holtek Semiconductor, HT49CV5 Datasheet - Page 15

• Manufacturer Part Number: HT49CV5
• Description: A/D
• Manufacturer: Holtek Semiconductor

The RTCC register descriptions are listed below.
Power Down Operation - HALT
The HALT mode is initialized by the HALT instruction
and results in the following.
The system can leave the HALT mode by means of an
external reset, an interrupt, an external falling edge sig-
nal on port A, an external rising/falling edge on the RMT
pin, or a WDT overflow. An external reset will initialize a
chip reset and a WDT overflow will initialize a warm re-
set . After examining the TO and PDF flags, the source
of the reset can be determined. The PDF flag is cleared
by a system power-up or by executing the CLR WDT
instruction, and is set by executing the HALT instruc-
tion. The TO flag is set if a WDT time-out occurs, and
causes a wake-up that only resets the Program Counter
and SP, the other flags remain in their original status.
The port A wake-up and interrupt methods can be con-
sidered as a continuation of normal execution. Each bit
in port A can be independently selected to wake up the
device by options. Awakening from an I/O port stimulus,
the program will resume execution at the next instruc-
tion. If the system is woken up via an interrupt, two pos-
sibilities may occur. If the related interrupt is disabled or
the interrupt is enabled but the stack is full, the program
will resume execution at the next instruction. But if the
Rev. 1.20
The system oscillator turns off but the WDT oscillator
keeps running (if the WDT oscillator or the real time
clock is selected).
The contents of the on-chip RAM and of the registers
remain unchanged.
The WDT is cleared and starts recounting (if the WDT
clock source is from the WDT oscillator or the real time
clock oscillator).
All I/O ports maintain their original status.
The PDF flag is set but the TO flag is cleared.
The VFD driver keeps running (if the RTC OSC is se-
lected).
Bit No.
3, 5~7
0~2
4
RT0~RT2
QOSC
Label
Read/
Write
R/W
R/W
Reset
1
0
8 to 1 multiplexer control inputs to select the real clock prescaler output
Unused bit, read as 0
32768Hz OSC quick start-up oscillator
0/1: quick/slow start
RTCC (09H) Register
Real Time Clock
15
interrupt is enabled and the stack is not full, the regular
interrupt response takes place.
If an interrupt request flag is set to 1 before entering
the HALT mode, the wake-up function of the related in-
terrupt will be disabled.
If a wake-up event occurs, it takes 1024 t
clock period) to resume normal operation. In other
words, a dummy period will be inserted after a wake-up.
If the wake-up results from an interrupt acknowledge
signal, the actual interrupt subroutine execution will be
delayed by one or more cycles. However, if the wake-up
results in the next instruction execution, this will be exe-
cuted immediately after the dummy period is finished.
To minimize power consumption, all the I/O pins should
be carefully managed before entering the HALT mode.
Reset
There are three ways in which a microcontroller reset
can occur, through events occurring both internally and
externally:
The WDT time-out reset during HALT is a little different
from other kinds of reset. Most of the conditions remain
unchanged except that the program counter and stack
pointer will be cleared to 0 and the TO flag will be set to
1. Most registers are reset to the initial condition once
the reset conditions are met.
The different types of resets described affect the reset
flags in different ways. These flags, the PDF and TO
flags, are located in the status register and are con-
trolled by various microcontroller operations such as the
HALT function or Watchdog Timer.
RES is reset during normal operation
RES is reset during HALT
WDT time-out is reset during normal operation
Function
HT49RV5/HT49CV5
April 14, 2006
SYS
(system