HT49CV5 Holtek Semiconductor, HT49CV5 Datasheet - Page 22

• Manufacturer Part Number: HT49CV5
• Description: A/D
• Manufacturer: Holtek Semiconductor

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Rev. 1.20
SBDR: Serial bus data register
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Bit 3 (MLS): MSB or LSB (1/0) shift first control bit
Bit 2 (CSEN): serial bus selection signal enable/dis-
able (SCS), when CSEN=0, SCS is floating
Bit 1 (WCOL): this bit is set to 1 if data is written to
SBDR (TXRX buffer) when data is transferred ®
writing will be ignored if data is written to SBDR
(TXRX buffer) when data is transferred
Bit 0 (TRF): data transferred or data received ®
used to generate interrupt
Note: data receiving is still working when the MCU
Data written to SBDR ® write data to TXRX buffer
only
Data read from SBDR ® read from SBDR only
Operating Mode description
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Disable: SCK, SDI, SCS floating, SDO output
high
Master transmitter: clock sending and data I/O
started by writing SBDR
Master clock sending started by writing SBDR
Slave transmitter: data I/O started by clock re-
ceived
Slave receiver: data I/O started by clock received
enters the HALT mode
SIO Block Diagram
22
Clock Polarity=Rising Edge or Falling Edge
(Configuration Option)
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Serial interface operation
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Master mode operation
Step1: Select CKS and select M1, M0 = 00, 01, 10
Step2: Select CSEN, MLS (the same as the slave)
Step3: Set SBEN
Step4: Writing data to SBDR
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Step5: Check WCOL
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Step6: Check TRFor waiting for serial bus interrupt
Step7: Read data from SBDR
Step8: Clear TRF
Step9: Go to step 4
data is stored in TXRX buffer
output SCK and SCS signals
go to step 5
Note: SIO internal operation:
WCOL= 1, clear WCOL and go to step 4
WCOL= 0, go to step 6
* data stored in TXRX buffer, and SDI data
* data transferred, data in TXRX buffer is
is shifted into TXRX buffer
latched into SBDR
HT49RV5/HT49CV5
April 14, 2006