HT49CV5 Holtek Semiconductor, HT49CV5 Datasheet - Page 25
HT49CV5
Manufacturer Part Number
HT49CV5
Description
A/D
Manufacturer
Holtek Semiconductor
Datasheet
1.HT49CV5.pdf
(48 pages)
- Current page: 25 of 48
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In a (6+2) bits mode PWM cycle, the duty cycle of each
modulation cycle is shown in the table.
A (7+1) bits mode PWM cycle is divided into two modu-
lation cycles (modulation cycle0~modulation cycle 1).
Each modulation cycle has 128 PWM input clock period.
In a (7+1) bits PWM function, the contents of the PWM
register is divided into two groups. Group 1 of the PWM
register is denoted by DC which is the value of
PWM.7~PWM.1.
The group 2 is denoted by AC which is the value of
PWM.0.
Rev. 1.20
Modulation cycle i
Parameter
(i=0~3)
AC (0~3)
i<AC
i AC
Duty Cycle
DC + 1
DC
64
64
(6+2) PWM Mode
(7+1) PWM Mode
25
In a (7+1) bits mode PWM cycle, the duty cycle of each
modulation cycle is shown in the table.
The modulation frequency, cycle frequency and cycle
duty of the PWM output signal are summarized in the
following table.
f
f
SYS
SYS
Modulation Frequency
/64 for (6+2) bits mode
/128 for (7+1) bits mode
Modulation cycle i
Parameter
(i=0~1)
PWM
HT49RV5/HT49CV5
PWM Cycle
Frequency
AC (0~1)
f
SYS
i<AC
i AC
/256
April 14, 2006
PWM Cycle
Duty Cycle
[PWM]/256
DC + 1
Duty
128
128
DC
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