HT49CV5 Holtek Semiconductor, HT49CV5 Datasheet - Page 9

• Manufacturer Part Number: HT49CV5
• Description: A/D
• Manufacturer: Holtek Semiconductor

Stack Register - STACK
The stack register is a special part of the memory used
to save the contents of the Program Counter. The stack
is organized into 8 levels and is neither part of the data
nor part of the program, and is neither readable nor
writeable. Its activated level is indexed by a stack
pointer (SP) and is neither readable nor writeable. At the
start of a subroutine call or an interrupt acknowledg-
ment, the contents of the Program Counter is pushed
onto the stack. At the end of the subroutine or interrupt
routine, signaled by a return instruction (RET or RETI),
the contents of the Program Counter is restored to its
previous value from the stack. After a chip reset, the SP
will point to the top of the stack.
If the stack is full and a non-masked interrupt takes
place, the interrupt request flag is recorded but the ac-
knowledgment is still inhibited. Once the SP is decre-
mented (by RET or RETI), the interrupt is serviced. This
feature prevents stack overflow, allowing the program-
mer to use the structure easily. Likewise, if the stack is
full, and a CALL is subsequently executed, a stack
overflow occurs and the first entry is lost (only the most
recent 8 return addresses are stored).
Data Memory - RAM
The data memory (RAM) has a capacity of 231 8 bits,
and is divided into two functional groups, namely; spe-
cial function registers (39 8 bit) and general purpose
data memory (RAM bank contains 192 8 bits) most of
which are readable/writeable, but some are read only.
The special function registers are overlapped in any
banks.
The special function registers consist of an Indirect ad-
dressing register 0 (00H), a Memory pointer register 0
(MP0;01H), an Indirect addressing register 1 (02H), a
Memory pointer register 1 (MP1;03H), a Bank pointer
(BP;04H), an Accumulator (ACC;05H), a Program coun-
ter lower-order byte register (PCL;06H), a Table pointer
(TBLP;07H), a Table higher-order byte register
(TBLH;08H), a Real time clock control register
(RTCC;09H), a Status register (STATUS;0AH), an Inter-
rupt control register 0 (INTC0;0BH), a Timer/Event
Counter 0 (TMR0H:0CH; TMR0L:0DH), a Timer/Event
Counter 0 control register (TMR0C;0EH), a Timer/Event
Counter 1 (TMR1H:0FH;TMR1L:10H), a Timer/Event
Counter 1 control register (TMR1C; 11H), Interrupt con-
trol register 1 (INTC1;1EH), Serial Bus control register
(SBCR;1FH), Serial Bus data register (SBDR; 20H), Re-
mote timer control register (RMTC;21H), Remote con-
trol capture register 0 (RMT0;22H), Remote control
Rev. 1.20
lated instructions require two cycles to complete the
operation. These areas may function as normal pro-
gram memory depending upon user s requirements.
9
capture register 1 (RMT1;23H), Multi-function interrupt
status register (MFIS;29H), PWM data register
(PWM0;1AH, PWM1;1BH), the A/D result register
(ADR;25H), the A/D control register (ADCR;26H), the
A/D clock setting register (ACSR;27H), VFD control reg-
ister (VFDC; 28H), I/O registers (PA;12H, PB;14H,
PC;16H, PD;18H) and I/O control registers (PAC;13H,
PBC;15H, PCC;17H, PDC;19H).
RAM Mapping
HT49RV5/HT49CV5
April 14, 2006