ST486DX ST Microelectronics, ST486DX Datasheet
ST486DX
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ST486DX Summary of contents
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... ST486DX SMM PROGRAMMING MANUAL st 1 EDITION NOVEMBER 1994 ...
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GENERAL INDEX 1. SMM OVERVIEW 1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... SGS-Thomson SMM Features SMM operation within one of the SGS-Thomson ST486DX microprocessors is similar to related operations performed by other x86 microprocessors. All processors with SMM capability, switch into real mode upon entry into the SMM interrupt handler. Each CPU has a unique SMM code lo- cations ...
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... ST486DX - SMM OVERVIEW 1.3 Typical SMM Routines A typical SMM routine is illustrated in the flowchart shown in Figure 1-1. Upon entry to SMM, the CPU registers that will be used by the SMM routine, must be saved. The SMM environment is initialized by setting up an Interrupt Descriptor Table, initializing segment limits and setting up a stack ...
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... SMM address space, the MMAC bit (CCR1, bit 3) must be set. This allows ADS# strobes to be generated for data accesses in memory which overlap SMM memory while in SMM mode not possible to execute code in main memory that overlaps SMM space while in SMM mode. ST486DX - SMM IMPLEMENTATION 13 ...
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... Configuration Control Registers This section describes how to use the Configuration Control Registers in SMM code. For a com- plete description of the Configuration Control Registers, refer to the SGS-Thomson ST486DX and ST486DX2 Processors Data Book. All Configuration Control Register bits are set to 0 when RESET is asserted. Asserting WM_RST does not affect the configuration registers ...
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... MMAC bit. Code fetches from the SMM address region always generate an SMADS# output and access SMM memory. If both the SMAC and MMAC bits are set to 1, the MMAC bit has precedence. ST486DX - SMM IMPLEMENTATION Register INDEX = C1h 4 ...
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... ST486DX - SMM IMPLEMENTATION Table CCR2 SUSP BWRT BARB WT1 HALT Suspend on HALT. HALT = 0: CPU does not enter suspend mode following execution of a HLT instruction HALT = 1: CPU enters suspend mode following execution of a HLT instruction. SUSP Enable Suspend Pins. ...
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... BLOCK SIZE 0h Disable 1h 4 KBytes 2h 8 KBytes 3h 16 KBytes 4h 32 KBytes 5h 64 KBytes 6h 128 KBytes 7h 256 KBytes ST486DX - SMM IMPLEMENTATION Reg. Index = CEh Reg. Index = CFh 0 7 A16 A15 A12 Bits 3-0 BLOCK SIZE 8h 512 KBytes 9h 1 MBytes Ah 2 MBytes Bh 4 MBytes ...
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... ST486DX - SMM IMPLEMENTATION 2.3 SMM Instruction Summary SGS-Thomson has added seven new instructions to the X86 standard instruction set to aid in SMM programming. These instructions are only valid when: CPL = 0 and SMI is enabled (CCR1 bit and SMAR size > 0 and either [in SMM mode or SMAC is on (CCR1 bit 2 =1)] The CPU will generate an undefined opcode fault when the above conditions are not met and one of the SMM instructions are executed ...
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... SMINT will cause the CPU to enter SMM as though the hardware SMI# pin was sampled low. The S bit in the SMM header is set. The SMI# signal is not driven by the CPU when SMM is en- tered with SMINT. ST486DX - SMM IMPLEMENTATION Parameters Core Clocks mem80 ...
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... ST486DX - SMM IMPLEMENTATION 2.3.6 SVDC - Save Register and Descriptor Instruction Opcode SVDC 0F 78 [mod sreg3 r/m] SVDC saves the contents of a segment register/selector and its associated descriptor to memory at mem80. This instruction can be used on any segment/selector including the Code Segment. 2.3.7 SVLDT - Save LDT and Descriptor ...
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... ST486DX - SMM SOFTWARE CONSIDERATIONS ;SMM SIZE is 16K ;index SMAR, SMM baseA31-A24 ;select ;set high SMM address to 00 ;write value ;index SMAR,SMM baseA23-A16 ;select ;set mid SMM address to 06h ;write value ;SMAR,SMM baseA15-A12 & SIZE ...
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... ST486DX - SMM SOFTWARE CONSIDERATIONS out 22h, al mov al, 083h out 23h, al mov al, 0c1h out 22h al, 23h mov ah, al mov al, 0c1h out 22h, al mov al al, SMI or SMAC; set SMI and SMAC out 23h, al mov ax, SMMBASE shr 4 mov es, ax mov edi, 0 mov ...
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... It is possible to save all the CPU registers as needed. See Section 3.3 for an example saving and re- storing the entire CPU state. 31 Top of SMM Address Space 31 Reserved 31 I/O Write Data Size Figure SMM Memory Space Header ST486DX - SMM SOFTWARE CONSIDERATIONS DR7 EFLAGS CR0 Current IP Next Selector CS Descriptor (Bits 63-32) CS Descriptor (Bits 31-0) 3 ...
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... ST486DX - SMM SOFTWARE CONSIDERATIONS Unique to the SGS-Thomson CPU is that the CPU saves the previous EIP (CURRENT_IP), before the SMI event, and the next EIP (NEXT_IP) that will be executed after exiting the SMI handler. Upon execution of an RSM instruction, control is returned to the NEXT_IP. The value of the NEXT_IP may need to be modified for restarting I/O instructions ...
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... SMM base specified by SMAR, CS limit is set to 4 GBytes EIP 0000 0000h; Begins execution at the base of SMM memory EFLAGS 0000 0002h; Reset State CR0 6000 0010h; Real Mode, Cache in Write Through DR7 0000 0400h; Traps disabled ST486DX - SMM SOFTWARE CONSIDERATIONS I/O Write I/O Write Address Data ...
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... ST486DX - SMM SOFTWARE CONSIDERATIONS 3.3 Maintaining the CPU State The following registers are not automatically saved/restored on SMM entry/exit. General Purpose Registers: EAX, EBX, ECX, EDX Pointer and Index Registers: EBP, ESI, EDI, ESP Selector/Segment Registers: DS, ES, SS, FS, GS Descriptor Table Registers: GDTR, IDTR, LDTR, TR ...
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... CPU state the Code Segment for this example save_ds dt ? save_es dt ? save_fs dt ? save_gs dt ? save_ss dt ? save_ldt dt ? save_tsr dt ? save_eax dd ? save_ebx dd ? save_ecx dd ? save_edx dd ? save_esi dd ? save_edi dd ? save_ebp dd ? save_esp dd ? save_gdt df ? save_idt df ? ST486DX - SMM SOFTWARE CONSIDERATIONS ;str is not valid in real mode ;32bit version saves everything ;32bit version saves everything 29 ...
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... ST486DX - SMM SOFTWARE CONSIDERATIONS 3.3.2 Maintaining Control Registers CR0 is maintained in the SMM header. CR2 and CR3 need only be saved if the SMM routine will be entering protected mode and enabling paging. Most SMM routines will not need to enable pag- ing. However, if the CPU is going to be powered off, these registers like all the others need to be saved ...
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... The protected mode application could have set a segment limit to less than 64K. To avoid a protection error, all segment registers can be given limits of 4 GBytes. This can be done with the SGS Thomson RSDC instruction and will allow access to the ST486DX - SMM SOFTWARE CONSIDERATIONS ;set the PE bit in CR0 ;clear the prefetch que ...
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... ST486DX - SMM SOFTWARE CONSIDERATIONS full 4-GBytes of possible system memory without entering protected mode. Once the limits of a segment register are set, the base can be changed by use of the MOV instruction. An Interrupt Descriptor Table (IDT) needs to be set up in SMM memory before any interrupts or exceptions occur ...
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... REP instruction ST486DX - SMM SOFTWARE CONSIDERATIONS ;select CCR1 ;get CCR1 current value ;save it ;select CCR1 again ;set MMAC ;write new value to CCR1 ;select CCR1 ...
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... ST486DX - SMM SOFTWARE CONSIDERATIONS bt ax,2 adc ecx,0 test al,1 shl 1 jnz out_instr ; A port read (INS or IN) instruction caused the ; chipset to generate an SMI instruction. ; Restore EDI from SMM header. mov edi, dword ptr cs:[SMI_ESIEDI] jmp common1 ; A port write (OUTS or OUT) instruction caused the ; chipset to generate an SMI instruction. ...
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... ST486DX - SMM SOFTWARE CONSIDERATIONS ;FS is base=0 limit=4G data ;segment to be used to check if ;HLT instruction was executing ;can’ HLT but could be ;a LOOP or REP ;decrement to HLT instruction ;save lin addr in edx ;if no paging then linear ...
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... ST486DX - SMM SOFTWARE CONSIDERATIONS mov al,cl or al,08h mov al,0c1h out 23h,al mov eax,CR3 and eax,0fffff000h mov ebx,edx shr ebx,22 ;read Directory Table mov eax,dword ptr fs:[eax+ebx*4] and eax,0fffff000h mov ebx,edx shr ebx,12 and ebx,03ffh mov eax,dword ptr fs:[eax+ebx*4] and eax,0fffff000h mov ebx,edx ...
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... I/O instruction. The only registers that are restored from the SMM header are CS, NEXT_IP, EFLAGS, CR0, and DR7. All other registers which were modified by the SMM program need to be restored before executing the RSM instruction. ST486DX - SMM SOFTWARE CONSIDERATIONS ;set MMAC back to normal ;was it a HLT instruction? ...
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... ST486DX - SMM SOFTWARE CONSIDERATIONS 3.10 Testing and Debugging SMM Code An SMI routine can be debugged with standard debugging tools (such as DOS DEBUG) if the following requirements are met: 1. The debugger will only be able to set a code break point using INT 3 outside of the SMI han- dler. The debug control register DR7 is set to the reset value upon entry to the SMI handler. ...
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... The typical current (I duced by approximately 50% when operating at 3.3 instead of 5.0 volts. Operating the CPU at 3.3 volts can reduce CPU power consumption by over 70%, as the power consumption increases as the square of the power supply voltage (P-=-V ST486DX - SMM POWER MANAGEMENT FEATURES Typical Curr ent Options ( (MHz)) + 150 mA @ 5.0 V ...
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... ST486DX - SMM POWER MANAGEMENT FEATURES 4.3 Suspend Mode The SGS-Thomson CPU allows suspend mode to be entered either through software or hardware. The software initiates suspend mode through execution of a HLT instruction if CCR2 bit 3 (HALT) is set. After the HLT instruction is executed, the CPU enters suspend mode and asserts the suspend acknowledge (SUSPA#) pin (if the SUSP bit in CCR2 was set to enable the SUSPA# pin) ...
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... ST486DX - ASSEMBLER MACROS FOR SGS-THOMSON INSTRUCTIONS A. ASSEMBLER MACROS FOR SGS-THOMSON INSTRUCTIONS The include file SMICAM.INC provides a complex set of macros which generate SMM opcodes along with the appropriate mod/rm bytes. In order to function, the macros require that the labels which are accessed correspond to the specified segment. Thus segment overrides must be passed to the macro as an argument ...
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... ST486DX - ASSEMBLER MACROS FOR SGS-THOMSON INSTRUCTIONS count=count+1 endif if (count eq 0) nop endif place1 = $ ;pull off the proper prefix byte count mov word ptr segover addr,reg org place1+count mov word ptr segover addr,reg place2 = $ ;patch the opcode org place1+(count*2)-1 db 0Fh,op org ...
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... ST486DX - ASSEMBLER MACROS FOR SGS-THOMSON INSTRUCTIONS SMI_CR0 EQU ($CR0 SMI_EFLAGS EQU ($EFLAGS + SMMSIZE - SIZE SMI_SAVE) SMI_DR7 EQU ($DR7 SMM Instruction macro example: TEST.ASM 0000 0000 0A*(??) 000A 0000 004E 0006 004E 000C 004E 0012 0000004E ...
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Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its ...