ST486DX ST Microelectronics, ST486DX Datasheet - Page 5

• Manufacturer Part Number: ST486DX
• Description: PROGRAMMING MANUAL
• Manufacturer: ST Microelectronics

2.
2.1
2.1.1
The signals at the SMI# and SMADS# pins are used to implement SMM. The SMI# pin is bi-direc-
tional. The SMI# pin is used by the chipset to signal the CPU that an SMI has occurred. While the
CPU is in the process of servicing an SMI interrupt, the SMI# pin is an output used to signal the
chipset that the SMM processing is occurring. The SMADS# address strobe signal is generated in-
stead of an ADS# address strobe signal while executing or accessing data in SMM address space.
2.1.2
To enter SMM mode, the SMI# signal must be asserted for at least one CLK period (Two clocks if
SMI# is asserted asynchronously). To accomplish I/O trapping, the SMI# signal should be asserted
two clocks before the RDY# for that I/O cycle. Once the CPU recognizes the active SMI# input,
the CPU drives the SMI input low for the duration of the SMI routine. The SMI routine is termi-
nated with an SMI specific resume instruction (RSM). When the RSM instruction is executed, the
CPU drives the SMI pin high for one CLK period. The SMI# pin must be allowed to go high for
one CLK at the end of the SMI routine in order for the next SMI to be recognized. Since the SMI#
pin is bi-directional, not more than one SMI# interrupt can become active at one time.
2.1.3
The CPU has two address strobes, ADS# and SMADS#. ADS# is the address strobe used during
normal operations. The SMADS# address strobe replaces ADS# during SMM for memory ac-
cesses when data is written, read, or fetched in the SMM defined region. Using a separate address
strobe increases chipset compatibility and control.
During an SMM interrupt routine, control can be transferred to main memory via a JMP, CALL,
Jcc instruction, execution of a software interrupt (INT), or a hardware interrupt (INTR or NMI).
Execution in main memory will cause ADS# to be generated for code and data outside of the de-
fined SMM address region. (It is assumed, but not required, that the chipset ultimately translates
SMADS# and a particular address to some other address.) To access data in main memory that
overlaps the SMM address space, the MMAC bit (CCR1, bit 3) must be set. This allows ADS#
strobes to be generated for data accesses in memory which overlap SMM memory while in SMM
mode. It is not possible to execute code in main memory that overlaps SMM space while in SMM
mode.
SGS-Thomson SMM IMPLEMENTATION
Hardware Background
SMM Pins
SMI# Pin Timing
Address Strobes
ST486DX - SMM IMPLEMENTATION
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