ST486DX ST Microelectronics, ST486DX Datasheet - Page 6

• Manufacturer Part Number: ST486DX
• Description: PROGRAMMING MANUAL
• Manufacturer: ST Microelectronics

ST486DX - SMM IMPLEMENTATION
SMADS# can also be generated for memory reads/writes and code fetches within the defined SMM
region when the SMAC bit (CCR1, bit 2) is set while in normal mode. The generation of SMADS#
permits a program in normal mode to jump into SMM code space. The RSM instruction should not
be executed after jumping into SMM space unless valid return information is first written into the
SMM header.
2.1.4
The SGS Thomson CPU has one RDY# input. Chipsets that implement the dual ready lines (one
for SMM and one for normal memory) can logically OR the two ready lines together to produce a
single RDY# line.
2.1.5
SMM memory is never cached in the CPU internal cache. This makes cache coherency completely
transparent to the SMM programmer. If the CPU cache is in write-back mode, all write-back cy-
cles will be directed to normal memory with the use of the ADS# signal. An INVD or WBINVD
will write dirty data out to normal memory even if it overlaps with SMM space.
SMM memory can be cached by a external cache controller, but it is up to the cache designer to be
sure to maintain a distinction between SMM memory space and normal memory space.
The A20M# input to the CPU is ignored for all SMM space accesses (any accesses which uses
SMADS#).
2.2
This section describes how to use the Configuration Control Registers in SMM code. For a com-
plete description of the Configuration Control Registers, refer to the SGS-Thomson ST486DX and
ST486DX2 Processors Data Book.
All Configuration Control Register bits are set to 0 when RESET is asserted. Asserting WM_RST
does not affect the configuration registers.
These registers are accessed by writing the register index to I/O port 22h. I/O port 23h is used for
data transfer. Each data transfer to I/O port 23h must be preceded by an I/O port 22h register index
selection, otherwise the port 23h access will be directed off chip. Before accessing these registers,
all interrupts, including SMI, must be disabled. A problem could occur if an interrupt occurs after
writing to port 22h but before accessing port 23h. The interrupt service routine might access port
22h or 23h. After returning from the interrupt, the access to port 23h would be redirected to an-
other index or possibly off chip. Before accessing the Configuration Control Registers from out-
side of SMM mode, the chipset generation of SMI# interrupt must be disabled if the CPU SMI#
input is enabled.
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Chipset RDY#
Cache Coherency
Configuration Control Registers