ST486DX ST Microelectronics, ST486DX Datasheet - Page 8

• Manufacturer Part Number: ST486DX
• Description: PROGRAMMING MANUAL
• Manufacturer: ST Microelectronics

ST486DX - SMM IMPLEMENTATION
Table 2 - 2
HALT
HALT = 0:
HALT = 1:
SUSP
SUSP = 0:
SUSP = 1:
Table 2 - 1
SMI_LOCK SMM Register Lock.
SMI_LOCK = 0: Any program in normal mode, as well as SMM software, has access to all
SMI_LOCK = 1: The following Configuration Control Register bits can not be modified unless
NMIEN
NMIEN = 0:
NMIEN = 1:
16
SUSP
7
7
Reserved
BWRT
Suspend on HALT.
Enable Suspend Pins.
NMI Enable.
6
6
CCR2
CCR3
CPU does not enter suspend mode following execution of a HLT instruction
CPU enters suspend mode following execution of a HLT instruction.
SUSP# input is ignored and SUSPA# output floats.
SUSP# input and SUSPA# output are enabled.
Configuration Control Registers.
operating in SMM mode:
SMI, SMAC, MMAC, NMIEN, SMI_LOCK, and SMAR register size fields.
NMI (Non-Maskable Interrupt) is not recognized during SMM. One occurrence of
NMI is latched and serviced after SMM mode is exited. The NMIEN bit should
be cleared before executing a RSM instruction to exit SMM.
NMI is enabled during SMM. This bit should only be set temporarily while in the
SMM routine to allow NMI interrupts to be serviced. NMIEN should not be set
BARB
5
5
WT1
4
4
Reg. INDEX = C2h
Reg. INDEX = C3h
HALT
3
3
LOCK-NW
2
2
NMIEN
WBAK
1
1
COP/Reserved
SMI-LOCK
0
0