ST486DX ST Microelectronics, ST486DX Datasheet - Page 10

• Manufacturer Part Number: ST486DX
• Description: PROGRAMMING MANUAL
• Manufacturer: ST Microelectronics

ST486DX - SMM IMPLEMENTATION
2.3.1
2.3
SGS-Thomson has added seven new instructions to the X86 standard instruction set to aid in SMM
programming. These instructions are only valid when:
CPL = 0 and
SMI is enabled (CCR1 bit 1 = 1) and
SMAR size > 0 and
either [in SMM mode or SMAC is on (CCR1 bit 2 =1)]
The CPU will generate an undefined opcode fault when the above conditions are not met and one
of the SMM instructions are executed. The assembly language macro SMIMAC.INC listed in Ap-
pendix A will automatically generate the appropriate machine code when included in a source file
containing SGS-Thomson SMM instructions.
Most of the SGS-Thomson SMM instructions are used to access the non-programmer visible inter-
nal descriptors. The standard x86 instructions can not access this information inside the CPU. This
information is stored in memory in a 10 Byte area that is comprised of both the descriptor (8-Bytes)
and the segment register/selector (2 Bytes). The 8 Byte descriptor is in the same format that is
found in the GDT or LDT. If the data area is dword aligned, it will minimize the memory access
time.
Table 2 - 5.
RSDC loads the information at the mem80 into a segment register/selector and its associated de-
scriptor. Attempting to use this instruction to load the Code Segment or Code Selector will gener-
ate an invalid opcode instruction. Code Segment or Code Selector is restored from the SMM
header as part of the RSM instruction.
18
15
P
Instruction
14
RSDC
DPL
RSDC - Restore Register and Descriptor
SMM Instruction Summary
13
Register and Descriptor Save Format
BASE 31 - 24
DT
12
0F 79 [mod sreg3 r/m]
11
Opcode
10
TYPE
SELECTOR or SEGMENT
9
LIMIT 15 - 0
BASE 15 - 0
8
G
7
sreg3, mem80
Parameters
D
6
0
5
BASE 23 - 16
AVL
4
3
Core Clocks
LIMIT 19 - 16
10
2
1
0
+8
+6
+4
+2
+0