DSP56F826 Motorola, DSP56F826 Datasheet - Page 13

• Manufacturer Part Number: DSP56F826
• Description: 16-bit Digital Signal Processor
• Manufacturer: Motorola

All inputs have a weak internal pull-up circuit associated with them. These pull-up circuits are always enabled.
Exceptions:
GPIOF0-
GPIOC4
GPIOF3
1.
2.
Signal
TA0-3
Name
TRST
STFS
TCK
TDO
TMS
Table 3. DSP56F826 Signal and Package Information for the 100 Pin LQFP
TCS
TDI
When a pn is owned by GPIO, then the pull-up may be disabled under software control.
TCK has a weak pull-down circuit always active.
Pin No.
100
55
91
90
89
88
99
2
3
1
4
Input
Input/Output
Input/Output
Input/Output
Input
Input
Output
Input
Input
Type
DSP56F826 Preliminary Technical Data
SSI Serial Transmit Frame Sync (STFS)—This bidirectional pin is used
by the Transmit section of the SSI as frame sync I/O or flag I/O. The STFS
can be used by both the transmitter and receiver in synchronous mode. It is
used to synchronize data transfer and can be an input or output pin.
Port C GPIO—This is a General Purpose I/O (GPIO) pin with the capability
of being individually programmed as input or output.
After reset, the default state is GPIO input.
TA0–3—Timer F Channels 0, 1, 2, and 3
Port F GPIO—These four General Purpose I/O (GPIO) pins can be
individually programmed as input or output.
After reset, the default state is Quad Timer.
TCS—This pin is reserved for factory use. It must be tied to V
use. In block diagrams, this pin is considered an additional V
Test Clock Input—This input pin provides a gated clock to synchronize the
test logic and shift serial data to the JTAG/OnCE port. The pin is connected
internally to a pull-down resistor.
Test Data Input—This input pin provides a serial input data stream to the
JTAG/OnCE port. It is sampled on the rising edge of TCK and has an on-
chip pull-up resistor.
Test Data Output—This tri-statable output pin provides a serial output data
stream from the JTAG/OnCE port. It is driven in the Shift-IR and Shift-DR
controller states, and changes on the falling edge of TCK.
Test Mode Select Input—This input pin is used to sequence the JTAG TAP
controller’s state machine. It is sampled on the rising edge of TCK and has
an on-chip pull-up resistor.
Test Reset—As an input, a low signal on this pin provides a reset signal to
the JTAG TAP controller. To ensure complete hardware reset, TRST should
be asserted whenever RESET is asserted. The only exception occurs in a
debugging environment when a hardware DSP reset is required and it is
necessary not to reset the JTAG/OnCE module. In this case, assert RESET,
but do not assert TRST.
Description
SS.
SS
Introduction
for normal
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