DSP56F826 Motorola, DSP56F826 Datasheet - Page 26

• Manufacturer Part Number: DSP56F826
• Description: 16-bit Digital Signal Processor
• Manufacturer: Motorola

Operating Conditions:
Operating Conditions:
26
External reference crystal frequency for the PLL
PLL output frequency
PLL stabilization time
Frequency of operation (external clock driver)
Clock Pulse Width
External clock input rise time
External clock input fall time
External
1.
correctly. The PLL is optimized for 8MHz input crystal.
2.
Note: The midpoint is V
1.
2.
3.
4.
5.
Clock
An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work
This is the minimum time required after the PLL setup is changed to ensure reliable operation
See
The high or low pulse width must be no smaller than 6.25 ns or the chip will not function.
External clock input rise time is measured from 10% to 90%.
External clock input fall time is measured from 90% to 10%.
Parameters shown are guaranteed by design.
Figure 9
Table 12. External Clock Operation Timing Requirements
2, 5
Characteristic
V
V
Characteristic
10%
50%
90%
SSIO
SSIO
2
for details on using the recommended connection of an external clock driver.
=V
=V
IL
t
SS
SS
PW
4, 5
3, 5
+ (V
= V
= V
SSA
SSA
IH
Figure 11. External Clock Timing
– V
= 0 V, V
= 0 V, V
DSP56F826 Preliminary Technical Data
IL
)/2.
DDIO
DDIO
Table 13. PLL Timing
1
1
=3.0 to 3.6V, V
=3.0 to 3.6V, V
t
PW
f
t
t
t
PW
rise
fall
osc
Symbol
Symbol
DD
DD
f
t
f
plls
osc
op
= V
= V
DDA
DDA
= 2.25–2.75 V, T
= 2.25–2.75 V, T
Min
6.25
—
—
0
Min
t
40
—
2
fall
A
A
= –40 to +85 C, C
Typ
= –40 to +85 C, C
—
—
—
—
Typ
—
4
1
t
rise
Max
Max
80
—
80
10
3
3
6
L
L
50 pF, f
50 pF, f
10%
50%
90%
op
op
V
V
MHz
Unit
MHz
MHz
Unit
IH
IL
= 80 MHz
= 80 MHz
ns
ns
ns
ms