DSP56F826 Motorola, DSP56F826 Datasheet - Page 32

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DSP56F826

Manufacturer Part Number
DSP56F826
Description
16-bit Digital Signal Processor
Manufacturer
Motorola
Datasheet

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Operating Conditions:
3.8 Serial Peripheral Interface (SPI) Timing
1.Parameters listed are guaranteed by design.
32
Characteristic
Cycle time
Master
Slave
Enable lead time
Master
Slave
Enable lag time
Master
Slave
Clock (SCLK) high time
Master
Slave
Clock (SCLK) low time
Master
Slave
Data setup time required for inputs
Master
Slave
Data hold time required for inputs
Master
Slave
Access time (time to data active from high-impedance state)
Slave
Disable time (hold time to high-impedance state)
Slave
Data Valid for outputs
Master
Slave (after enable edge)
Data invalid
Master
Slave
Rise time
Master
Slave
Fall time
Master
Slave
V
SSIO
=V
SS
= V
SSA
= 0 V, V
DSP56F826 Preliminary Technical Data
DDIO
Table 16. SPI Timing
=3.0 to 3.6V, V
DD
Symbol
= V
t
t
t
t
t
ELD
ELG
t
t
t
DH
t
t
DV
t
CH
CL
DS
t
t
DI
C
A
D
R
F
DDA
= 2.25–2.75 V, T
1
Min
17.6
24.1
100
4.8
3.7
50
50
25
25
25
20
0
0
2
0
0
A
= –40 to +85 C, C
Max
15.2
20.4
11.5
10.0
4.5
9.7
9.0
15
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
L
50 pF, f
See Figure
Figures 19,
Figures 19,
Figures 19,
Figures 19,
Figures 19,
Figures 19,
Figures 19,
Figures 19,
Figures 19,
20, 21,
20, 21,
20, 21,
20, 21,
20, 21,
20, 21,
20, 21,
20, 21,
20, 21,
Figure
Figure
Figure
Figure
op
= 80 MHz
22
22
22
22
22
22
22
22
22
22
22
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