DS2182A Dallas Semiconducotr, DS2182A Datasheet - Page 16
DS2182A
Manufacturer Part Number
DS2182A
Description
T1 Line Monitor
Manufacturer
Dallas Semiconducotr
Datasheet
1.DS2182A.pdf
(25 pages)
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193E RECEIVE MULTIFRAME TIMING Figure 15
NOTES:
1. Signaling data is updated during signaling frames on channel boundaries. Pin RABCD is the LSB of
2. RLINK data (FDL data) is updated one bit-time prior to odd frames and held for two frames.
RECEIVE MULTIFRAME BOUNDARY TIMING Figure 16
NOTES:
1. RLINK timing is shown for 193E; in 193S, RLINK is updated on even frame boundaries and is held
2. Total delay from RPOS and RNEG to RSER output is 13 RCLK periods.
each channel word in non-signaling frames.
across multiframe edges.
16 of 25
DS2182A
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