IDT72V245L15TF IDT, Integrated Device Technology Inc, IDT72V245L15TF Datasheet

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IDT72V245L15TF

Manufacturer Part Number
IDT72V245L15TF
Description
IC FIFO SYNC 4096X18 15NS 64QFP
Manufacturer
IDT, Integrated Device Technology Inc
Series
72Vr
Datasheet

Specifications of IDT72V245L15TF

Function
Synchronous
Memory Size
72K (4K x 18)
Access Time
15ns
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
64-STQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Data Rate
-
Other names
72V245L15TF

Available stocks

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Manufacturer
Quantity
Price
Part Number:
IDT72V245L15TF
Manufacturer:
IDT
Quantity:
2
Part Number:
IDT72V245L15TF
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
IDT72V245L15TF8
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IDT, Integrated Device Technology Inc
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10 000
Part Number:
IDT72V245L15TFGI
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IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
IDT72V245L15TFI
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
IDT72V245L15TFI8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
FEATURES:
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FUNCTIONAL BLOCK DIAGRAM
IDT, IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
©2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
(HF)/WXO
256 x 18-bit organization array (IDT72V205)
512 x 18-bit organization array (IDT72V215)
1,024 x 18-bit organization array (IDT72V225)
2,048 x 18-bit organization array (IDT72V235)
4,096 x 18-bit organization array (IDT72V245)
10 ns read/write cycle time
5V input tolerant
IDT Standard or First Word Fall Through timing
Single or double register-buffered Empty and Full flags
Easily expandable in depth and width
Asynchronous or coincident Read and Write Clocks
Asynchronous or synchronous programmable Almost-Empty
and Almost-Full flags with default settings
Half-Full flag capability
Output enable puts output data bus in high-impedanc state
High-performance submicron CMOS technology
Available in a 64-lead thin quad flatpack (TQFP/STQFP)
RXO
WXI
RXI
RS
FL
EXPANSION LOGIC
WRITE CONTROL
WRITE POINTER
WEN
RESET LOGIC
LOGIC
WCLK
3.3 VOLT CMOS SyncFIFO
256 x 18, 512 x 18, 1,024 x 18,
2,048 x 18, and 4,096 x 18
OE
1,024 x 18, 2,048 x 18
OUTPUT REGISTER
INPUT REGISTER
256 x 18, 512 x 18
RAM ARRAY
4,096 x 18
Q0-Q17
D0-D17
1
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DESCRIPTION:
patible versions of the IDT72205LB/72215LB/72225LB/72235LB/72245LB,
designed to run off a 3.3V supply for exceptionally low power consumption.
These devices are very high-speed, low-power First-In, First-Out (FIFO)
memories with clocked read and write controls. These FIFOs are applicable
for a wide variety of data buffering needs, such as optical disk controllers, Local
Area Networks (LANs), and interprocessor communication.
by a free-running clock (WCLK), and an input enable pin (WEN). Data is read
into the synchronous FIFO on every clock when WEN is asserted. The output
port is controlled by another clock pin (RCLK) and another enable pin (REN).
The Read Clock(RCLK) can be tied to the Write Clock for single clock operation
or the two clocks can run asynchronous of one another for dual-clock operation.
An Output Enable pin (OE) is provided on the read port for three-state control
of the output.
Industrial temperature range (–40° ° ° ° ° C to +85° ° ° ° ° C) is available
Green parts available, see ordering information
The IDT72V205/72V215/72V225/72V235/72V245 are functionally com-
These FIFOs have 18-bit input and output ports. The input port is controlled
TM
OFFSET REGISTER
READ CONTROL
READ POINTER
RCLK
LOGIC
LOGIC
FLAG
IDT72V205, IDT72V215,
IDT72V225, IDT72V235,
REN
OCTOBER 2008
LD
IDT72V245
4294 drw 01
EF/OR
PAE
FF/IR
PAF
HF/(WXO)
DSC-4294/6

Related parts for IDT72V245L15TF

IDT72V245L15TF Summary of contents

Page 1

FEATURES: • • • • • 256 x 18-bit organization array (IDT72V205) • • • • • 512 x 18-bit organization array (IDT72V215) • • • • • 1,024 x 18-bit organization array (IDT72V225) • • • • • 2,048 ...

Page 2

IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 DESCRIPTION (CONTINUED) The synchronous FIFOs have two fixed flags, Empty Flag/Output Ready (EF/OR) and Full Flag/Input Ready (FF/IR), and two ...

Page 3

IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 PIN DESCRIPTION Symbol Name D0–D17 Data Inputs I RS Reset I WCLK Write Clock I WEN Write Enable I RCLK ...

Page 4

IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 ABSOLUTE MAXIMUM RATINGS Symbol Rating V (2) Terminal Voltage TERM with respect to GND T Storage STG Temperature I DC ...

Page 5

IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 ELECTRICAL CHARACTERISTICS (Commercial: VCC = 3.3V ± 0.3V 0°C to +70°C; Industrial: VCC = 3.3V ± 0.3V, ...

Page 6

IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 FUNCTIONAL DESCRIPTION TIMING MODES: IDT STANDARD vs FIRST WORD FALL THROUGH (FWFT) MODE The IDT72V205/72V215/72V225/72V235/72V245 support two different timing modes ...

Page 7

IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 The contents of the offset registers can be read on the data output lines Q when the LD pin is ...

Page 8

IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 TABLE 3 — TRUTH TABLE FOR CONFIGURATION AT RESET FL RXI WXI EF/ Single register-buffered Empty Flag ...

Page 9

IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 SIGNAL DESCRIPTIONS: INPUTS: DATA Data inputs for 18-bit wide data. CONTROLS: RESET (RS) ...

Page 10

IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 When the LD pin is LOW and WEN is HIGH, the WCLK input is disabled; then a signal at this ...

Page 11

IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 REN, WEN, LD (1) FL, RXI, WXI (2) RCLK, WCLK FF/IR EF/OR PAF, WXO/ HF, RXO PAE Q - ...

Page 12

IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 RCLK t t ENS ENH REN OLZ OE WCLK WEN NOTES: is ...

Page 13

IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 WRITE WCLK (1) t SKEW1 WEN RCLK t ENS t ENH REN OE ...

Page 14

IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 CLK t t CLKH CLKL WCLK t ENS LD t ENS WEN ...

Page 15

IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 CLKH WCLK WEN PAF words in FIFO RCLK REN NOTES PAF ...

Page 16

IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 WCLK WXO t ENS WEN NOTE: 1. Write to Last Physical Location. RCLK RXO t ENS REN NOTE: 1. Read ...

Page 17

IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 COMMERCIAL AND INDUSTRIAL TM 17 TEMPERATURE RANGES OCTOBER 22, 2008 ...

Page 18

IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 COMMERCIAL AND INDUSTRIAL TM 18 TEMPERATURE RANGES OCTOBER 22, 2008 ...

Page 19

IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 CLKH CLKL WCLK t ENH t ENS WEN n words in FIFO (2) , PAE n + 1words ...

Page 20

IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 WRITE WCLK 1 (1) t SKEW1 WEN RCLK t ENH t ENS REN ...

Page 21

IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 RCLK t t ENH ENS REN t REF OLZ t OE ...

Page 22

IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 OPERATING CONFIGURATIONS SINGLE DEVICE CONFIGURATION A single IDT72V205/72V215/72V225/72V235/72V245 may be used when the application requirements are for 256/512/1,024/2,048/4,096 words or ...

Page 23

IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 DEPTH EXPANSION CONFIGURATION — DAISY CHAIN TECHNIQUE (WITH PROGRAMMABLE FLAGS) These devices can easily be adapted to applications requiring more ...

Page 24

IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 DEPTH EXPANSION CONFIGURATION (FWFT MODE) In FWFT mode, the FIFOs can be connected in series (the data outputs of one ...

Page 25

ORDERING INFORMATION XXXXX X XX Device Type Power Speed Package NOTES: 1. Industrial temperature range product for the 15ns speed grade is available as a standard device. All other speed grades are available by special order. 2. Green parts are ...

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