KSZ8893-MQL Micrel Semiconductor, Inc., KSZ8893-MQL Datasheet - Page 36

• Manufacturer Part Number: KSZ8893-MQL
• Description: Integrated 3-Port 10/100 Managed Switch with PHYs
• Manufacturer: Micrel Semiconductor, Inc.

Serial Management Interface (SMI)
The SMI is the KSZ8893MQL non-standard MIIM interface that provides access to all KSZ8893MQL configuration
registers. This interface allows an external device to completely monitor and control the states of the
KSZ8893MQL.
The SMI interface consists of the following:
The following table depicts the SMI frame format.
SMI register read access is selected when OP Code is set to “00” and bit 4 of the PHY address is set to ‘1’. SMI
register write access is selected when OP Code is set to “00” and bit 4 of the PHY address is set to ‘0’. PHY
address bit[3] is undefined for SMI register access, and hence can be set to either ‘0’ or ‘1’ in read/write
operations.
To access the KSZ8893MQL registers 0-141 (0x00 – 0x8D), the following applies:
SMI register access is the same as the MIIM register access, except for the register access requirements
presented in this section.
Repeater Mode
The KSZ8893MQL supports repeater mode in 100BASE-TX Half Duplex mode. In repeater mode, all ingress
packets are broadcast to the other two ports. MAC address checking and learning are disabled.
Repeater mode is enabled by setting register 6 bit[7] to ‘1’. Prior to setting this bit, all three ports need to be
configured to 100BASE-TX Half Duplex mode. Additionally, both PHY ports need to have auto-negotiation
disabled.
The latency between the two PHY ports is 270 ns (minimum) and 310 ns (maximum). The 40 ns difference is one
clock skew (one 25 MHz clock period) between reception and transmission. Latency is defined as the time from
the first bit of the Destination Address (DA) entering the ingress port to the first bit of the DA exiting the egress
port.
Micrel
November 2005
Read
Write
PHYAD[2:0] and REGAD[4:0] are concatenated to form the 8-bit address;
that is, {PHYAD[2:0], REGAD[4:0]} = bits [7:0] of the 8-bit address.
Registers are 8 data bits wide.
A physical connection that incorporates the data line (MDIO) and the clock line (MDC).
A specific protocol that operates across the aforementioned physical connection that allows an external
controller to communicate with the KSZ8893MQL device.
Access to all KSZ8893MQL configuration registers. Register access includes the Global, Port and
Advanced Control Registers 0-141 (0x00 – 0x8D), and indirect access to the standard MIIM registers
[0:5] and custom MIIM registers [29, 31].
For read operation, data bits [15:8] are read back as 0’s.
For write operation, data bits [15:8] are not defined, and hence can be set to either ‘0’ or ‘1’.
Preamble
32 1’s
32 1’s
Start of
Frame
01
01
Table 8. Serial Management Interface (SMI) Frame Format
00
Read/Write
OP Code
00
0xRRR
PHY
Address
Bits [4:0]
1xRRR
36
REG
Address
Bits [4:0]
RRRRR
RRRRR
TA
Z0
10
xxxx_xxxx_DDDD_DDDD
Data
Bits [15:0]
0000_0000_DDDD_DDDD
KSZ8893MQL/MQLI
M9999-111705
Idle
Z
Z