KSZ8893-MQL Micrel Semiconductor, Inc., KSZ8893-MQL Datasheet - Page 9

• Manufacturer Part Number: KSZ8893-MQL
• Description: Integrated 3-Port 10/100 Managed Switch with PHYs
• Manufacturer: Micrel Semiconductor, Inc.

List of Figures
Figure 1. Typical Straight Cable Connection ......................................................................................................................................24
Figure 2. Typical Crossover Cable Connection ..................................................................................................................................25
Figure 3. Auto-Negotiation and Parallel Operation ............................................................................................................................26
Figure 4. Destination Address Lookup Flow Chart, Stage 1 .............................................................................................................29
Figure 5. Destination Address Resolution Flow Chart, Stage 2 .......................................................................................................30
Figure 6. 802.1p Priority Field Format .................................................................................................................................................41
Figure 7. KSZ8893MQL EEPROM Configuration Timing Diagram....................................................................................................43
Figure 8. SPI Write Data Cycle..............................................................................................................................................................45
Figure 9. SPI Read Data Cycle ..............................................................................................................................................................46
Figure 10. SPI Multiple Write.................................................................................................................................................................46
Figure 11. SPI Multiple Read.................................................................................................................................................................46
Figure 12: Far-End Loopback Path ......................................................................................................................................................47
Figure 13. Near-end (Remote) Loopback Path....................................................................................................................................48
Figure 14. EEPROM Interface Input Timing Diagram .........................................................................................................................94
Figure 15. EEPROM Interface Output Timing Diagram ......................................................................................................................94
Figure 16. SNI Input Timing Diagram...................................................................................................................................................95
Figure 17. SNI Output Timing Diagram................................................................................................................................................95
Figure 18. MAC Mode MII Timing – Data Received from MII..............................................................................................................96
Figure 19. MAC Mode MII Timing – Data Input to MII .........................................................................................................................96
Figure 20. PHY Mode MII Timing – Data Received from MII ..............................................................................................................97
Figure 21. PHY Mode MII Timing – Data Input to MII ..........................................................................................................................97
Figure 22: RMII Timing – Data Received from RMII............................................................................................................................98
Figure 23: RMII Timing – Data Input to RMII........................................................................................................................................98
Figure 24. SPI Input Timing...................................................................................................................................................................99
Figure 25. SPI Output Timing..............................................................................................................................................................100
Figure 26: Auto-Negotiation Timing...................................................................................................................................................101
Figure 27. Reset Timing ......................................................................................................................................................................102
Figure 28. Recommended Reset Circuit............................................................................................................................................103
Figure 29. Recommended Reset Circuit for interfacing with CPU/FPGA Reset Output...............................................................103
Figure 30. 128-Pin PQFP Package......................................................................................................................................................105
Micrel
November 2005
9
KSZ8893MQL/MQLI
M9999-111705