KSZ8893-MQL Micrel Semiconductor, Inc., KSZ8893-MQL Datasheet - Page 83

• Manufacturer Part Number: KSZ8893-MQL
• Description: Integrated 3-Port 10/100 Managed Switch with PHYs
• Manufacturer: Micrel Semiconductor, Inc.

Registers 118 to 120
Registers 118 to 120 are User Defined Registers (UDRs). These are general purpose read/write registers that can
be used to pass user defined control and status information between the KSZ8893MQL and the external
processor.
Register 118 (0x76): User Defined Register 1
Bit
7-0
Register 119 (0x77): User Defined Register 2
Bit
7-0
Register 120 (0x78): User Defined Register 3
Bit
7-0
Registers 121 to 131
Registers 121 to 131 provide read and write access to the static MAC address table, VLAN table, dynamic MAC
address table, and MIB counters.
Register 121 (0x79): Indirect Access Control 0
Bit
7-5
4
3-2
1-0
Register 122 (0x7A): Indirect Access Control 1
Bit
7-0
Note: A write to register 122 triggers the read/write command. Read or write access is determined by register 121 bit 4.
Register 123 (0x7B): Indirect Data Register 8
Bit
7
6-3
2-0
Micrel
November 2005
Name
UDR1
Name
UDR2
Name
UDR3
Name
Reserved
Read High /
Write Low
Table Select
Indirect
Address High
Name
Indirect
Address Low
Name
CPU Read
Status
Reserved
Indirect Data
[66:64]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
Description
Description
Description
Description
Reserved
Do not change the default values.
= 1, read cycle
= 0, write cycle
00 = static MAC address table selected
01 = VLAN table selected
10 = dynamic MAC address table selected
11 = MIB counter selected
Bits [9:8] of indirect address
Description
Bits [7:0] of indirect address
Description
This bit is applicable only for dynamic MAC
address table and MIB counter reads.
= 1, read is still in progress
= 0, read has completed
Reserved
Bits [66:64] of indirect data
83
Default
0x00
Default
0x00
Default
0x00
Default
000
0
00
00
Default
0000_0000
Default
0
0000
000
KSZ8893MQL/MQLI
M9999-111705