KSZ8893-MQL Micrel Semiconductor, Inc., KSZ8893-MQL Datasheet - Page 61

• Manufacturer Part Number: KSZ8893-MQL
• Description: Integrated 3-Port 10/100 Managed Switch with PHYs
• Manufacturer: Micrel Semiconductor, Inc.

Register 13 (0x0D): Global Control 11
Bit
7-6
5-4
3-2
1-0
Register 14 (0x0E): Global Control 12
Bit
7
6-3
2-0
Register 15 (0x0F): Global Control 13
Bit
7-3
2-0
Micrel
November 2005
Name
Tag_0x7
Tag_0x6
Tag_0x5
Tag_0x4
Name
Unknown
Packet
Default
Port
Enable
Reserved
Unknown
Packet
Default
Port
Name
PHY
Address
Reserved
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
Description
IEEE 802.1p mapping. The value in this field is used as
the frame’s priority when its IEEE 802.1p tag has a value
of 0x7.
IEEE 802.1p mapping. The value in this field is used as
the frame’s priority when its IEEE 802.1p tag has a value
of 0x6.
IEEE 802.1p mapping. The value in this field is used as
the frame’s priority when its IEEE 802.1p tag has a value
of 0x5.
IEEE 802.1p mapping. The value in this field is used as
the frame’s priority when its IEEE 802.1p tag has a value
of 0x4.
Description
Send packets with unknown destination MAC addresses to
specified port(s) in bits [2:0] of this register.
0 = disable
1 = enable
Reserved
Do not change the default values.
Specify which port(s) to send packets with unknown
destination MAC addresses. This feature is enabled by bit
[7] of this register.
An ‘1’ includes a port.
An ‘0’ excludes a port.
Description
00000 : N/A
00001 : Port 1 PHY address is 0x1
00010 : Port 1 PHY address is 0x2
…
11101 : Port 1 PHY address is 0x29
11110 : N/A
11111 : N/A
Note:
Port 2 PHY address = (Port 1 PHY address) + 1
Reserved
Do not change the default values.
Bit 2 stands for port 3.
Bit 1 stands for port 2.
Bit 0 stands for port 1.
61
Default
11
11
10
10
Default
0
0x0
111
Default
00001
000
KSZ8893MQL/MQLI
M9999-111705