IDT72V36102L10PF IDT, Integrated Device Technology Inc, IDT72V36102L10PF Datasheet - Page 12

• Manufacturer Part Number: IDT72V36102L10PF
• Description: IC FIFO 262KX18 10NS 120QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V36102L10PF

• Function: Synchronous
• Memory Size: 4.7Mb (262k x 18)
• Data Rate: 100MHz
• Access Time: 10ns
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 120-TQFP, 120-VQFP
• Configuration: Dual
• Density: 4.5Mb
• Access Time (max): 6.5ns
• Word Size: 36b
• Organization: 64Kx36x2
• Sync/async: Synchronous
• Expandable: No
• Bus Direction: Bi-Directional
• Package Type: TQFP
• Clock Freq (max): 100MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.15V
• Operating Supply Voltage (max): 3.45V
• Supply Current: 400mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 120
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V36102L10PF

SYNCHRONIZED FIFO FLAGS
This is done to improve flag signal reliability by reducing the probability of
metastable events when CLKA and CLKB operate asynchronously to one
another. EFA/ORA, AEA, FFA/IRA, and AFA are synchronized to CLKA. EFB/
ORB, AEB, FFB/IRB, and AFB are synchronized to CLKB. Tables 4 and 5 show
the relationship of each port flag to FIFO1 and FIFO2.
EMPTY/OUTPUT READY FLAGS (EFA/ORA, EFB/ORB)
ORB) function is selected. When the Output Ready flag is HIGH, new data is
present in the FIFO output register. When the Output Ready flag is LOW, the
previous data word is present in the FIFO output register and attempted FIFO
reads are ignored.
When the Empty Flag is HIGH, data is available in the FIFO’s RAM for reading
to the output register. When the Empty Flag is LOW, the previous data word is
present in the FIFO output register and attempted FIFO reads are ignored.
that reads data from its array. For both the FWFT and IDT Standard modes,
the FIFO read pointer is incremented each time a new word is clocked to its
TABLE 4 — FIFO1 FLAG OPERATION (IDT STANDARD AND FWFT MODES)
TABLE 5 — FIFO2 FLAG OPERATION (IDT STANDARD AND FWFT MODES)
NOTES:
1. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.
2. Data in the output register does not count as a "word in FIFO memory". Since in FWFT mode, the first word written to an empty FIFO goes unrequested to the output register (no
3. X2 is the Almost-Empty offset for FIFO2 used by AEA. Y2 is the Almost-Full offset for FIFO2 used by AFB. Both X2 and Y2 are selected during a reset of FIFO2 or programmed from
4. The ORA and IRB functions are active during FWFT mode; the EFA and FFB functions are active in IDT Standard mode.
NOTES:
1. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.
2. Data in the output register does not count as a "word in FIFO memory". Since in FWFT mode, the first word written to an empty FIFO goes unrequested to the output register (no
3. X1 is the Almost-Empty offset for FIFO1 used by AEB. Y1 is the Almost-Full offset for FIFO1 used by AFA. Both X1 and Y1 are selected during a reset of FIFO1 or programmed from
4. The ORB and IRA functions are active during FWFT mode; the EFB and FFA functions are active in IDT Standard mode.
IDT72V3682/72V3692/72V36102 3.3V CMOS SyncBiFIFO
16,384 x 36 x 2, 32,768 x 36 x 2 and 65,536 x 36 x 2
Each FIFO is synchronized to its port clock through at least two flip-flop stages.
These are dual purpose flags. In the FWFT mode, the Output Ready (ORA,
In the IDT Standard mode, the Empty Flag (EFA, EFB) function is selected.
The Empty/Output Ready flag of a FIFO is synchronized to the port clock
read operation necessary), it is not included in the FIFO memory count.
port A.
read operation necessary), it is not included in the FIFO memory count.
port A.
(X1+1) to [16,384-(Y1+1)]
(X2+1) to [16,384-(Y2+1)]
(16,384-Y1) to 16,383
(16,384-Y2) to 16,383
IDT72V3682
IDT72V3682
1 to X1
16,384
1 to X2
16,384
0
0
(3)
(3)
Number of Words in FIFO
Number of Words in FIFO
(X1+1) to [32,768-(Y1+1)]
(X2+1) to [32,768-(Y2+1)]
(32,768-Y1) to 32,767
(32,768-Y2) to 32,767
IDT72V3692
IDT72V3692
1 to X1
1 to X2
32,768
32,768
0
0
(3)
(3)
(1,2)
(1,2)
(X1+1) to [65,536-(Y1+1)]
(X2+1) to [65,536-(Y2+1)]
TM
(65,536-Y1) to 65,535
(65,536-Y2) to 65,535
IDT72V36102
IDT72V36102
1 to X1
1 to X2
65,536
65,536
12
0
0
output register. The state machine that controls an Output Ready flag monitors
a write pointer and read pointer comparator that indicates when the FIFO
memory status is empty, empty+1, or empty+2.
to the FIFO output register in a minimum of three cycles of the Output Ready
flag synchronizing clock. Therefore, an Output Ready flag is LOW if a word in
memory is the next data to be sent to the FlFO output register and three cycles
of the port Clock that reads data from the FIFO have not elapsed since the time
the word was written. The Output Ready flag of the FIFO remains LOW until
the third LOW-to-HIGH transition of the synchronizing clock occurs, simulta-
neously forcing the Output Ready flag HIGH and shifting the word to the FIFO
output register.
Flag will indicate the presence of data available for reading in a minimum of two
cycles of the Empty Flag synchronizing clock. Therefore, an Empty Flag is LOW
if a word in memory is the next data to be sent to the FlFO output register and
two cycles of the port Clock that reads data from the FIFO have not elapsed
since the time the word was written. The Empty Flag of the FIFO remains LOW
until the second LOW-to-HIGH transition of the synchronizing clock occurs,
forcing the Empty Flag HIGH; only then can data be read.
In FWFT mode, from the time a word is written to a FIFO, it can be shifted
In IDT Standard mode, from the time a word is written to a FIFO, the Empty
(3)
(3)
EFB/ORB
EFA/ORA
H
H
H
H
H
H
H
H
L
L
Synchronized
Synchronized
to CLKB
to CLKA
COMMERCIAL TEMPERATURE RANGE
AEB
AEA
H
H
H
H
H
H
L
L
L
L
AFA
AFB
H
H
H
H
H
H
L
L
Synchronized
L
L
Synchronized
to CLKA
to CLKB
FFA/IRA
FFB/IRB
H
H
H
H
H
H
H
H
L
L