IDT72V36102L10PF IDT, Integrated Device Technology Inc, IDT72V36102L10PF Datasheet - Page 4

• Manufacturer Part Number: IDT72V36102L10PF
• Description: IC FIFO 262KX18 10NS 120QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V36102L10PF

• Function: Synchronous
• Memory Size: 4.7Mb (262k x 18)
• Data Rate: 100MHz
• Access Time: 10ns
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 120-TQFP, 120-VQFP
• Configuration: Dual
• Density: 4.5Mb
• Access Time (max): 6.5ns
• Word Size: 36b
• Organization: 64Kx36x2
• Sync/async: Synchronous
• Expandable: No
• Bus Direction: Bi-Directional
• Package Type: TQFP
• Clock Freq (max): 100MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.15V
• Operating Supply Voltage (max): 3.45V
• Supply Current: 400mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 120
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V36102L10PF

PIN DESCRIPTIONS
IDT72V3682/72V3692/72V36102 3.3V CMOS SyncBiFIFO
16,384 x 36 x 2, 32,768 x 36 x 2 and 65,536 x 36 x 2
A0-A35
AEA
AEB
AFA
AFB
B0 - B35
CLKA
CLKB
CSA
CSB
EFA/ORA
EFB/ORB
ENA
ENB
FFA/IRA
FFB/IRB
FWFT
FS1, FS0
Symbol
Port A Data
Port A Almost-
Empty Flag
Port B Almost-
Empty Flag
Port A Almost-
Full Flag
Port B Almost-
Full Flag
Port B Data
Port A Clock
Port B Clock
Port A Chip
Select
Port B Chip
Select
Port A Empty/
Output Ready
Flag
Port B Empty/
Output Ready
Flag
Port A Enable
Port B Enable
Port A Full/
Input Ready
Flag
Port B Full/
Input Ready
Flag
First Word Fall
Through Mode
Flag Offset
Selects
Name
(Port A) less than or equal to the value in the Almost-Empty A Offset register, X2.
(Port B) less than or equal to the value in the Almost-Empty B Offset register, X1.
(Port A) FIFO1 is less than or equal to the value in the Almost-Full A Offset register, Y1.
(Port B) FIFO2 is less than or equal to the value in the Almost-Full B Offset register, Y2.
I/O
I/O
I/0
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
Programmable Almost-Empty flag synchronized to CLKA. It is LOW when the number of words in FIFO2 is
Programmable Almost-Empty flag synchronized to CLKB. It is LOW when the number of words in FIFO1 is
Programmable Almost-Full flag synchronized to CLKA. It is LOW when the number of empty locations in
Programmable Almost-Full flag synchronized to CLKB. It is LOW when the number of empty locations in
36-bit bidirectional data port for side B.
CLKA is a continuous clock that synchronizes all data transfers through port A and can be asynchronous or
coincident to CLKB. FFA/IRA, EFA/ORA, AFA, and AEA are all synchronized to the LOW-to-HIGH
transition of CLKA.
CLKB is a continuous clock that synchronizes all data transfers through port Band can be asynchronous or
coincident to CLKA. FFB/IRB, EFB/ORB, AFB, and AEB are synchronized to the LOW-to-HIGH
transition of CLKB.
CSA must be LOW to enable a LOW-to-HIGH transition of CLKA to read or write on port A. The A0-A35
outputs are in the high-impedance state when CSA is HIGH.
CSB must be LOW to enable a LOW-to-HIGH transition of CLKB to read or write data on port B. The
B0- B35 outputs are in the high-impedance state when CSB is HIGH.
whether or not the FIFO2 memory is empty. In the FWFT mode, the ORA function is selected. ORA
indicates the presence of valid data on A0-A35 outputs, available for reading. EFA/ORA is synchronized
to the LOW-to-HIGH transition of CLKA.
whether or not the FIFO1 memory is empty. In the FWFT mode, the ORB function is selected. ORB
indicates the presence of valid data on B0-B35 outputs, available for reading. EFB/ORB is synchronized to
the LOW-to-HIGH transition of CLKB.
ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on port A.
ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data on port B.
This is a dual function pin. In the IDT Standard mode, the FFA function is selected. FFA indicates
indicates whether or not there is space available for writing to the FIFO1 memory. FFA/IRA is
synchronized to the LOW-to-HIGH transition of CLKA.
This is a dual function pin. In the IDT Standard mode, the FFB function is selected. FFB indicates
whether or not the FIFO2 memory is full. In the FWFT mode, the IRB function is selected. IRB
indicates whether or not there is space available for writing to the FIFO2 memory. FFB/IRB is
synchronized to the LOW-to-HIGH transition of CLKB.
This pin selects the timing mode. A HIGH on FWFT selects IDT Standard mode, a LOW selects First
Word Fall Through mode. Once the timing mode has been selected, the level on FWFT must be static
throughout device operation.
A LOW-to-HIGH transition of the FIFO Reset input latches the values of FS0 and FS1. If either FS0 or
FS1 is HIGH when the FIFO Reset input goes HIGH, one of three preset values is selected as the
offset for FIFOs Almost-Full and Almost-Empty flags. If both FIFOs are reset simultaneously and both
FS0 and FS1 are LOW when RST1 and RST2 go HIGH, the first four writes to FIFO1 load the Almost-
Empty and Almost-Full offsets for both FIFOs.
36-bit bidirectional data port for side A.
This is a dual function pin. In the IDT Standard mode, the EFA function is selected. EFA indicates
This is a dual function pin. In the IDT Standard mode, the EFB function is selected. EFB indicates
whether or not the FIFO1 memory is full. In the FWFT mode, the IRA function is selected. IRA
TM
4
Description
COMMERCIAL TEMPERATURE RANGE