IDT72V36102L10PF IDT, Integrated Device Technology Inc, IDT72V36102L10PF Datasheet - Page 21

• Manufacturer Part Number: IDT72V36102L10PF
• Description: IC FIFO 262KX18 10NS 120QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V36102L10PF

• Function: Synchronous
• Memory Size: 4.7Mb (262k x 18)
• Data Rate: 100MHz
• Access Time: 10ns
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 120-TQFP, 120-VQFP
• Configuration: Dual
• Density: 4.5Mb
• Access Time (max): 6.5ns
• Word Size: 36b
• Organization: 64Kx36x2
• Sync/async: Synchronous
• Expandable: No
• Bus Direction: Bi-Directional
• Package Type: TQFP
• Clock Freq (max): 100MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.15V
• Operating Supply Voltage (max): 3.45V
• Supply Current: 400mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 120
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V36102L10PF

NOTE:
1. t
A0 - A35
IDT72V3682/72V3692/72V36102 3.3V CMOS SyncBiFIFO
16,384 x 36 x 2, 32,768 x 36 x 2 and 65,536 x 36 x 2
B0 -B35
CLKA edge is less than t
CLKA
SKEW1
CLKB
W/RB
ORB
W/RA
CSB
MBB
ENB
CSA
MBA
IRA
ENA
is the minimum time between a rising CLKB edge and a rising CLKA edge for IRA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising
LOW
HIGH
LOW
HIGH
FIFO1 Full
HIGH
LOW
Previous Word in FIFO1 Output Register
t
CLKH
SKEW1
t
CLK
, then IRA may transition HIGH one CLKA cycle later than shown.
t
Figure 12. IRA Flag Timing and First Available Write when FIFO1 is Full (FWFT Mode)
ENS2
t
CLKL
t
SKEW1
t
t
ENH
A
(1)
1
t
CLKH
TM
t
CLK
21
t
CLKL
2
Next Word From FIFO1
t
PIR
t
ENS2
t
ENS2
t
DS
COMMERCIAL TEMPERATURE RANGE
To FIFO1
Write
t
PIR
t
t
t
ENH
DH
ENH
4679 drw 15