IDT72V36102L10PF IDT, Integrated Device Technology Inc, IDT72V36102L10PF Datasheet - Page 24

• Manufacturer Part Number: IDT72V36102L10PF
• Description: IC FIFO 262KX18 10NS 120QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V36102L10PF

• Function: Synchronous
• Memory Size: 4.7Mb (262k x 18)
• Data Rate: 100MHz
• Access Time: 10ns
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 120-TQFP, 120-VQFP
• Configuration: Dual
• Density: 4.5Mb
• Access Time (max): 6.5ns
• Word Size: 36b
• Organization: 64Kx36x2
• Sync/async: Synchronous
• Expandable: No
• Bus Direction: Bi-Directional
• Package Type: TQFP
• Clock Freq (max): 100MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.15V
• Operating Supply Voltage (max): 3.45V
• Supply Current: 400mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 120
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V36102L10PF

NOTE:
1. t
NOTES:
1. t
2. FIFO1 Write (CSA = LOW, W/RA = LOW, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO1 output register has been read from the FIFO.
A0-A35
CLKA
CLKB
IDT72V3682/72V3692/72V36102 3.3V CMOS SyncBiFIFO
16,384 x 36 x 2, 32,768 x 36 x 2 and 65,536 x 36 x 2
ENA
AEB
ENB
CLKB edge is less than t
CLKB edge is less than t
CLKA
W/RA
B0-B35
SKEW1
SKEW2
MBA
ENA
CSA
EFA
CLKB
W/RB
MBB
CSB
ENB
FFB
is the minimum time between a rising CLKA edge and a rising CLKB edge for FFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising
is the minimum time between a rising CLKA edge and a rising CLKB edge for AEB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising
LOW
LOW
FIFO2 Full
LOW
LOW
HIGH
LOW
Previous Word in FIFO2 Output Register
t
CLKH
X1 Words in FIFO1
t
ENS2
SKEW1
SKEW2
Figure 15. FFB
Figure 16. Timing for AEB
, then FFB may transition HIGH one CLKB cycle later than shown.
, then AEB may transition HIGH one CLKB cycle later than shown.
t
CLK
t
ENS2
t
CLKL
FFB
FFB
FFB
FFB Flag Timing and First Available Write when FIFO2 is Full (IDT Standard Mode)
t
ENH
t
SKEW2
(1)
t
t
SKEW1
ENH
t
AEB
AEB
AEB when FIFO1 is Almost-Empty (IDT Standard and FWFT Modes)
AEB
A
1
(1)
1
t
CLKH
TM
t
CLK
24
t
CLKL
2
t
PAE
2
t
Next Word From FIFO2
PIR
t
t
ENS2
ENS2
t
DS
COMMERCIAL TEMPERATURE RANGE
To FIFO2
(X1+1) Words in FIFO1
Write
t
ENS2
t
PIR
t
t
t
DH
ENH
ENH
t
ENH
t
PAE
4679 drw 18
4679 drw 19