IDT72V36102L10PF IDT, Integrated Device Technology Inc, IDT72V36102L10PF Datasheet - Page 2

• Manufacturer Part Number: IDT72V36102L10PF
• Description: IC FIFO 262KX18 10NS 120QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V36102L10PF

• Function: Synchronous
• Memory Size: 4.7Mb (262k x 18)
• Data Rate: 100MHz
• Access Time: 10ns
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 120-TQFP, 120-VQFP
• Configuration: Dual
• Density: 4.5Mb
• Access Time (max): 6.5ns
• Word Size: 36b
• Organization: 64Kx36x2
• Sync/async: Synchronous
• Expandable: No
• Bus Direction: Bi-Directional
• Package Type: TQFP
• Clock Freq (max): 100MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.15V
• Operating Supply Voltage (max): 3.45V
• Supply Current: 400mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 120
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V36102L10PF

PIN CONFIGURATION
DESCRIPTION
supply for exceptionally low-power consumption. These devices are mono-
lithic, high-speed, low-power, CMOS Bidirectional SyncFIFO (clocked) memo-
ries which support clock frequencies up to 100MHz and have read access times
as fast as 6.5ns. Two independent 16,384/32,768/65,536 x 36 dual-port
SRAM FIFOs on board each chip buffer data in opposite directions. Commu-
nication between each port may bypass the FIFOs via two 36-bit mailbox
registers. Each mailbox register has a flag to signal when new mail has been
stored.
employs a synchronous interface. All data transfers through a port are gated
IDT72V3682/72V3692/72V36102 3.3V CMOS SyncBiFIFO
16,384 x 36 x 2, 32,768 x 36 x 2 and 65,536 x 36 x 2
The IDT72V3682/72V3692/72V36102 are designed to run off a 3.3V
These devices are a synchronous (clocked) FIFO, meaning each port
FWFT
GND
GND
V
V
V
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
CC
CC
CC
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
TQFP (PN120-1, order code: PF)
TM
TOP VIEW
2
to the LOW-to-HIGH transition of a port clock by enable signals. The clocks for
each port are independent of one another and can be asynchronous or
coincident. The enables for each port are arranged to provide a simple
bidirectional interface between microprocessors and/or buses with synchro-
nous control.
the first word written to an empty FIFO is deposited into the memory array. A
read operation is required to access that word (along with all other words
residing in memory). In the First Word Fall Through mode (FWFT), the first
long-word (36-bit wide) written to an empty FIFO appears automatically on the
outputs, no read operation required (Nevertheless, accessing subsequent
words does necessitate a formal read request). The state of the FWFT pin
during FIFO operation determines the mode in use.
These devices have two modes of operation: In the IDT Standard mode,
Each FIFO has a combined Empty/Output Ready Flag (EFA/ORA and EFB/
COMMERCIAL TEMPERATURE RANGE
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
4679 drw 03
B
B
B
B
GND
B
B
B
B
B
B
V
B
B
GND
B
B
B
B
B
B
GND
B
B
V
B
B
B
B
GND
35
34
33
32
31
30
29
28
27
26
CC
25
24
23
22
21
20
19
18
17
16
CC
15
14
13
12