IDT72V36102L10PF IDT, Integrated Device Technology Inc, IDT72V36102L10PF Datasheet - Page 17

• Manufacturer Part Number: IDT72V36102L10PF
• Description: IC FIFO 262KX18 10NS 120QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V36102L10PF

• Function: Synchronous
• Memory Size: 4.7Mb (262k x 18)
• Data Rate: 100MHz
• Access Time: 10ns
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 120-TQFP, 120-VQFP
• Configuration: Dual
• Density: 4.5Mb
• Access Time (max): 6.5ns
• Word Size: 36b
• Organization: 64Kx36x2
• Sync/async: Synchronous
• Expandable: No
• Bus Direction: Bi-Directional
• Package Type: TQFP
• Clock Freq (max): 100MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.15V
• Operating Supply Voltage (max): 3.45V
• Supply Current: 400mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 120
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V36102L10PF

NOTE:
1. t
IDT72V3682/72V3692/72V36102 3.3V CMOS SyncBiFIFO
16,384 x 36 x 2, 32,768 x 36 x 2 and 65,536 x 36 x 2
A0 - A35
B0 -B35
If the time between the rising CLKA edge and rising CLKB edge is less than t
cycle later than shown.
SKEW1
CLKA
CLKB
W/RB
WRA
MBA
ORB
MBB
CSA
ENA
CSB
ENB
IRA
is the minimum time between a rising CLKA edge and a rising CLKB edge for ORB to transition HIGH and to clock the next word to the FIFO1 output register in three CLKB cycles.
HIGH
FIFO1Empty
HIGH
LOW
LOW
HIGH
LOW
Figure 8. ORB Flag Timing and First Data Word Fall Through when FIFO1 is Empty (FWFT Mode)
t
t
ENS2
t
ENS2
DS
W1
t
Old Data in FIFO1 Output Register
SKEW1
t
t
t
ENH
DH
ENH
(1)
t
CLKH
1
t
CLK
t
CLKL
SKEW1
TM
, then the transition of ORB HIGH and load of the first word to the output register may occur one CLKB
17
2
t
CLKH
t
CLK
t
CLKL
t
POR
3
t
A
t
ENS2
COMMERCIAL TEMPERATURE RANGE
t
POR
t
ENH
W1
4679 drw 11