CS4382A Cirrus Logic, CS4382A Datasheet - Page 25

• Manufacturer Part Number: CS4382A
• Description: 192 kHz 8-Channel D/A Converter
• Manufacturer: Cirrus Logic

DS618PP1
3.8
3.9
3.9.1 Capacitor Placement
3.10
Direct Stream Digital (DSD) Mode
In stand-alone mode, DSD operation is selected by holding DSD_EN(LRCK) high and applying the DSD
data and clocks to the appropriate pins. The M[2:0] pins set the expected DSD rate and MCLK ratio.
In control-port mode the FM bits set the device into DSD mode (DSD_EN pin is not required to be held high).
The DIF register then controls the expected DSD rate and MCLK ratio.
During DSD operation, the PCM related pins should either be tied low or remain active with clocks (except
LRCK in Stand-alone mode). When the DSD related pins are not being used they should either be tied static
low, or remain active with clocks (except M3 in Stand-alone mode).
Grounding and Power Supply Arrangements
As with any high resolution converter, the CS4382A requires careful attention to power supply and ground-
ing arrangements if its potential performance is to be realized. The Typical Connection Diagram shows the
recommended power arrangements, with VA, VD, VLC, and VLS connected to clean supplies. If the ground
planes are split between digital ground and analog ground, the GND pins of the CS4382A should be con-
nected to the analog ground plane.
All signals, especially clocks, should be kept away from the FILT+ and VQ pins in order to avoid unwanted
coupling into the DAC.
Analog Output and Filtering
The application note “Design Notes for a 2-Pole Filter with Differential Input” discusses the second-order
Butterworth filter and differential to single-ended converter which was implemented on the CS4382A eval-
uation board, CDB4382A, as seen in Figure 16. The CS4382A does not include phase or amplitude com-
pensation for an external filter. Therefore, the DAC system phase and amplitude response will be dependent
on the external analog circuitry. The off-chip filter has been designed to attenuate the typical full-scale out-
put level to below 2 Vrms.
Figure 15 shows how the full-scale differential analog output level specification is derived.
Decoupling capacitors should be placed as close to the DAC as possible, with the low value ceramic ca-
pacitor being the closest. To further minimize impedance, these capacitors should be located on the same
layer as the DAC. If desired, all supply pins with similar voltage ratings may be connected to the same sup-
ply, but a decoupling capacitor should still be placed on each supply pin.
The CDB4382A evaluation board demonstrates the optimum layout and power supply arrangements.
Notes:
All decoupling capacitors should be referenced to analog ground.
CS4382A
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