CS4382A Cirrus Logic, CS4382A Datasheet - Page 32

• Manufacturer Part Number: CS4382A
• Description: 192 kHz 8-Channel D/A Converter
• Manufacturer: Cirrus Logic

32
5. REGISTER DESCRIPTION
Note: All registers are read/write in I
5.1
5.1.1 Control Port Enable (CPEN)
5.1.2 Freeze Controls (Freeze)
5.1.3 Master Clock DIVIDE ENABLE (mclkdiv)
5.1.4 DAC Pair Disable (DACx_DIS)
CPEN
0
7
Mode Control 1 (address 01h)
Default = 0
0 - Disabled
1 - Enabled
Function:
This bit defaults to 0, allowing the device to power-up in Stand-Alone mode. The Control port mode can be
accessed by setting this bit to 1. This will allow the operation of the device to be controlled by the registers
and the pin definitions will conform to Control Port Mode. To accomplish a clean power-up, the user should
write this bit within 10 ms following the release of Reset.
Default = 0
0 - Disabled
1 - Enabled
Function:
This function allows modifications to be made to the registers without the changes taking effect until the
FREEZE is disabled. To make multiple changes in the Control port registers take effect simultaneously, en-
able the FREEZE Bit, make all register changes, then Disable the FREEZE bit.
Default = 0
0 - Disabled
1 - Enabled
Function:
The MCLKDIV bit enables a circuit which divides the externally applied MCLK signal by 2 prior to all other
internal circuitry.
Default = 0
0 - Enabled
1 - Disabled
Function:
When enabled the respective DAC channel pairx (AOUTAx and AOUTBx) will remain in a reset state. It is
advised that changes to these bits be made while the power down bit is enabled to eliminate the possibility
of audible artifacts.
FREEZE
6
0
MCLKDIV
5
0
2
C mode and write only in SPI, unless otherwise noted.
DAC4_DIS
0
4
DAC3_DIS
3
0
DAC2_DIS
2
0
DAC1_DIS
0
1
CS4382A
DS618PP1
PDN
0
1