SC16C852L NXP Semiconductors, SC16C852L Datasheet - Page 11

• Manufacturer Part Number: SC16C852L
• Description: 16 mode or 68 mode bus interface
• Manufacturer: NXP Semiconductors

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NXP Semiconductors
Table 2.
[1]
6. Functional description
SC16C852L_3
Product data sheet
Symbol
LOWPWR 12
16/68
n.c.
HVQFN32 package die supply ground is connected to both V
ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be
soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias
need to be incorporated in the PCB in the thermal pad region.
Pin description
Pin
LQFP48
24
25, 37
HVQFN32 TFBGA36
9
17
-
The SC16C852L provides serial asynchronous receive data synchronization,
parallel-to-serial and serial-to-parallel data conversions for both the transmitter and
receiver sections. These functions are necessary for converting the serial data stream into
parallel data that is required with digital data systems. Synchronization for the serial data
stream is accomplished by adding start and stop bits to the transmit data to form a data
character (character orientated protocol). Data integrity is ensured by attaching a parity bit
to the data character. The parity bit is checked by the receiver for any transmission bit
errors. The electronic circuitry to provide all these functions is fairly complex, especially
when manufactured on a single integrated silicon chip. The SC16C852L represents such
an integration with greatly enhanced features. The SC16C852L is fabricated with an
advanced CMOS process.
The SC16C852L is an upward solution to the SC16C652B that provides a dual UART
capability with 128 bytes of transmit and receive FIFO memory, instead of 32 bytes for the
SC16C652 and 16 bytes in the SC16C2550. The SC16C852L is designed to work with
high speed modems and shared network environments that require fast data processing
time. Increased performance is realized in the SC16C852L by the transmit and receive
FIFOs. This allows the external processor to handle more networking tasks within a given
time. In addition, the four selectable receive and transmit FIFO trigger interrupt levels are
provided in SC16C652 mode, or 128 programmable levels are provided in the extended
mode for maximum data throughput performance especially when operating in a
multi-channel environment (see
memory greatly reduces the bandwidth requirement of the external controlling CPU and
increases performance. A low power pin (LOWPWR) is provided to further reduce power
consumption by isolating the host bus interface.
…continued
D3
F6
A4, B4,
B5, E4
1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder
Type
I
I
-
Rev. 03 — 18 January 2008
Description
Low Power. When asserted (active HIGH), the device immediately
goes into low power mode. The oscillator is shut-off and some host
interface pins are isolated from the host’s bus to reduce power
consumption. The device only returns to normal mode when the
LOWPWR pin is de-asserted. On the negative edge of a
de-asserting LOWPWR signal, the device is automatically reset
and all registers return to their default reset states. This pin has an
internal pull-down resistor, therefore, it can be left unconnected.
Bus select. Intel or Motorola bus select.
When 16/68 pin is at logic 1 or left unconnected (internally
pulled-up) the device will operate in Intel bus type of interface.
When 16/68 pin is at logic 0, the device will operate in Motorola
bus type of interface.
not connected
SS
Section 6.2 “Extended mode (128-byte
pin and exposed center pad. V
SS
pin must be connected to supply
SC16C852L
FIFO)”). The FIFO
© NXP B.V. 2008. All rights reserved.
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