SC16C852L NXP Semiconductors, SC16C852L Datasheet - Page 38

• Manufacturer Part Number: SC16C852L
• Description: 16 mode or 68 mode bus interface
• Manufacturer: NXP Semiconductors

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NXP Semiconductors
SC16C852L_3
Product data sheet
7.17 Flow Control Trigger Level High (FLWCNTH)
7.18 Flow Control Trigger Level Low (FLWCNTL)
7.19 Clock Prescaler (CLKPRES)
[1]
This 8-bit register is used to store the receive FIFO high threshold levels to start/stop
transmission during hardware/software flow control.
bit settings; see
Table 29.
[1]
This 8-bit register is used to store the receive FIFO low threshold levels to start/stop
transmission during hardware/software flow control.
settings; see
Table 30.
[1]
This register hold values for the clock prescaler.
Table 31.
Bit
7:0
Bit
7:0
Bit
7:4
3:0
For 32-byte FIFO mode, refer to
For 32-byte FIFO mode, refer to
For 32-byte FIFO mode, refer to
Symbol
FLWCNTH[7:0]
Symbol
FLWCNTL[7:0]
Symbol
CLKPRES[7:4]
CLKPRES[3:0]
FLWCNTH register bits description
FLWCNTL register bits description
Clock Prescaler register bits description
Section
Section
1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder
6.5.
Rev. 03 — 18 January 2008
6.5.
Description
This register stores the programmable HIGH threshold level for
hardware and software flow control for 128-byte FIFO mode
Description
This register stores the programmable LOW threshold level for
hardware and software flow control for 128-byte FIFO mode
Description
reserved
Clock Prescaler value. Reset to 0.
0x00 = trigger level is set to 1
0x01 = trigger level is set to 1
...
0x80 = trigger level is set to 128
0x00 = trigger level is set to 1
0x01 = trigger level is set to 1
...
0x80 = trigger level is set to 128
Section
Section
Section
7.3.
7.3.
7.3.
Table 30
Table 29
shows FLWCNTL register bit
shows FLWCNTH register
SC16C852L
© NXP B.V. 2008. All rights reserved.
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