SC16C852L NXP Semiconductors, SC16C852L Datasheet - Page 40

• Manufacturer Part Number: SC16C852L
• Description: 16 mode or 68 mode bus interface
• Manufacturer: NXP Semiconductors

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NXP Semiconductors
SC16C852L_3
Product data sheet
7.22 Advanced Feature Control Register 1 (AFCR1)
Table 34.
[1]
Bit
7
6:5
4
3
2
1
0
It takes 4 XTAL1 clocks to reset the device.
Symbol
AFCR1[7]
AFCR1[6:5]
AFCR1[4]
AFCR1[3]
AFCR1[2]
AFCR1[1]
AFCR1[0]
Advanced Feature Control Register 1 register bits description
1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder
Rev. 03 — 18 January 2008
Description
Concurrent write. When this bit is set the host can write concurrently to
the same register of all channel.
logic
reserved
Sleep RXLow. Program RX input to be edge-sensitive or level-sensitive.
reserved
RTS/CTS mapped to DTR/DSR. Switch the function of RTS/CTS to
DTR/DSR.
SReset. Software Reset
TSR Interrupt. Select TSR interrupt mode
logic 0 = Normal operation
logic 1 = Concurrent Write operation
logic 0 = RX input is level-sensitive. If RXA/RXB pin is LOW, the UART
will not go to sleep. Once the UART is in Sleep mode, it will wake up if
RXA/RXB pin goes LOW.
logic 1 = RX input is edge-sensitive. UART will go to sleep even if
RXA/RXB pin is LOW, and will wake up when RXA/RXB pin toggles.
logic 0 = RTS and CTS signals are used for hardware flow control.
logic 1 = DTR and DSR signals are used for hardware flow control.
RTS and CTS retain their functionality.
A write to this bit will reset the UART. Once the UART is reset this bit is
automatically set to 0.
logic 0 = transmit empty interrupt occurs when transmit FIFO falls
below the trigger level or becomes empty.
logic 1 = transmit empty interrupt occurs when transmit FIFO falls
below the trigger level, or becomes empty and the last stop bit has
been shifted out of the Transmit Shift Register.
[1]
SC16C852L
© NXP B.V. 2008. All rights reserved.
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