SC16C852L NXP Semiconductors, SC16C852L Datasheet - Page 31

• Manufacturer Part Number: SC16C852L
• Description: 16 mode or 68 mode bus interface
• Manufacturer: NXP Semiconductors

w w w . D a t a S h e e t . i n
NXP Semiconductors
SC16C852L_3
Product data sheet
7.5 Line Control Register (LCR)
The Line Control Register is used to specify the asynchronous data communication
format. The word length, the number of stop bits, and the parity are selected by writing the
appropriate bits in this register.
Table 17.
Table 18.
Table 19.
Table 20.
Bit
7
6
5:3
2
1:0
LCR[5]
X
X
0
0
1
LCR[2]
0
1
1
LCR[1]
0
0
1
1
Symbol
LCR[7]
LCR[6]
LCR[5:3]
LCR[2]
LCR[1:0]
Line Control Register bits description
LCR[5:3] parity selection
LCR[2] stop bit length
LCR[1:0] word length
LCR[4]
X
0
1
0
1
Word length (bits)
5, 6, 7, 8
5
6, 7, 8
LCR[0]
0
1
0
1
Description
Divisor latch enable. The internal baud rate counter latch and Enhanced
Feature mode enable.
Set break. When enabled, the Break control bit causes a break condition to
be transmitted (the TX output is forced to a logic 0 state). This condition
exists until disabled by setting LCR[6] to a logic 0.
Programs the parity conditions (see
Stop bits. The length of stop bit is specified by this bit in conjunction with the
programmed word length (see
Word length bits 1, 0. These two bits specify the word length to be
transmitted or received (see
1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder
Rev. 03 — 18 January 2008
LCR[3]
0
1
1
1
1
logic 0 = divisor latch disabled (normal default condition)
logic 1 = divisor latch enabled
logic 0 = no TX break condition (normal default condition)
logic 1 = forces the transmitter output (TX) to a logic 0 for alerting the
remote receiver to a line break condition
logic 0 or cleared = default condition
logic 0 or cleared = default condition
Word length (bits)
5
6
7
8
Stop bit length (bit times)
1
1
2
Parity selection
no parity
odd parity
even parity
forced parity ‘1’
forced parity ‘0’
1
2
Table
Table
20).
Table
19).
18).
SC16C852L
© NXP B.V. 2008. All rights reserved.
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