LV24250LS Sanyo Semicon Device, LV24250LS Datasheet - Page 7

• Manufacturer Part Number: LV24250LS
• Description: 1-Chip FM Tuner IC
• Manufacturer: Sanyo Semicon Device

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Format of Bus Transfers
Bus transfers are primarily based on the I
Start, restart, and stop conditions are specified as shown in Table 1 below.
For details, like timing, etc., refer to specifications of I
8-bit write
Read is of the same form as write, only except that the data direction is opposite.
Eight data bits are sent from LV24250LS to the master while Ack is sent from the master to LV24250LS.
The serial clock SCL is supplied from the master side. It is essential that data bit is output from LV24250LS in
synchronization with the falling edge while the master side performs latching at the rising edge.
• Start condition
• Repeated start condition
• Stop condition
• Byte write
• Byte read
8-bit data is sent from the master microcomputer to LV24250LS.
Data bit consists of MSB first and LSB last.
Data transmission is latched at the rising edge of SCL in synchronization with the SCL clock generated at the master IC.
Do not change data while SCL remains HIGH.
LV24250LS outputs the ACK bit between eighth and ninth falling edges of SCL
SDA
SCL
SDA
SCL
SDA
SCL
Start
D7
D7
Fig. 1 the I
D6
D6
Fig. 2 Signal pattern of the I
Fig. 3 Signal pattern of the I
2
C primitives
2
C start, repeated start and stop conditions.
D5
D5
SDA
LV24250LS
SCL
D4
D4
Repeated start
2
C.
D3
D3
2
2
C byte write
D2
C byte read
D2
D1
D1
D0
SDA
SCL
D0
Ack
Stop
Ack
No.A1699-7/18
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