LV24250LS Sanyo Semicon Device, LV24250LS Datasheet - Page 8

• Manufacturer Part Number: LV24250LS
• Description: 1-Chip FM Tuner IC
• Manufacturer: Sanyo Semicon Device

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LV24250LS latches ACK at the rising edge.
The sequence to write data D into the register A of LV24250LS is shown below.
When one or more data has been provided for writing, only the first data is allowed to be written.
Read sequence
Interrupt Pin INT
LV24250LS has the dedicated interrupt output pin. For the active level to the host, either LOW or HIGH can be selected.
The INT output pin is kept floating while the PWRAD bit is cleared during initialization.
Therefore, to avoid influence on the CPU side during initialization, it is recommended to secure the non-active state by
means of the pull-up or pull-down resistor.
This enables direct INT output connection to non-masking interruption of the host CPU.
• Start condition
• write the device address (C0h)
• write the register address, A
• write the target data, D
• stop condition
• start condition
• write the device address (C0h)
• write the register address, A
• repeated start condition (or stop + start in a single master network)
• write the device address + 1 (C1h)
• read the register contents D, transmit NACK (no more data to be read)
• stop condition
SDA
SCL
SDA
SCL
start
start
start
DA7
A7
DA7
write register address
write device address + 1
DA7
DA6...1
write device address
A6...1
DA6...1
write device address
Fig. 4 Register write through I
Fig. 5 Register read through I
DA6...1
LV24250LS
Ack
Ack
Ack
D7
Ack
D7
write data byte
read data byte with NACK
D6...0
A7
write register address
2
2
C
C
D6...0
A6...0
Ack
Ack
stop
stop
rep.
No.A1699-8/18
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