ds96-039wdsp ETC-unknow, ds96-039wdsp Datasheet
ds96-039wdsp
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ds96-039wdsp Summary of contents
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... Document Number DSP1620 DS97-321WDSP DSP1627 DS96-188WDSP DSP1628 DS97-040WDSP DSP1629 DS96-039WDSP Table 2 shows a corrected description of the CLK/CLK1/CLK2 field of the serial I/O control register. The specific correction is shown in bold type—the active clock frequency is a ratio of f Table 2. Corrected Description of CLK/CLK1/CLK2 Field Field Value CLK ...
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... Lucent Technologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No rights under any patent accompany the sale of any such product(s) or information. Copyright © 1999 Lucent Technologies Inc. All Rights Reserved May 1999 AY99-001WDSP (must accompany DS97-321WDSP , DS96-188WDSP , DS97-040WDSP , and DS96-039WDSP) ...
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Preliminary Data Sheet February 1997 1 Features Optimized for digital cellular applications with a bit manipulation unit for higher coding efficiency and an error correction coprocessor for equalization and channel coding support. On-chip, programmable, PLL clock synthesizer. 19.2 ns and ...
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DSP1628 Digital Signal Processor Contents 1 Features ...................................................................1 2 Description ...............................................................1 3 Pin Information .........................................................3 4 Hardware Architecture..............................................8 4.1 DSP1628 Architectural Overview.......................8 4.2 DSP1600 Core Architectural Overview ............12 4.3 Interrupts and Trap...........................................13 4.4 Memory Maps and Wait-States........................18 4.5 External Memory ...
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February 1997 3 Pin Information DB4 15 DB3 16 DB2 17 DB1 18 DB0 ERAMHI ERAMLO 23 EROM 24 25 RWN EXM 27 AB15 28 AB14 29 ...
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DSP1628 Digital Signal Processor 3 Pin Information (continued DB4 3 DB3 4 DB2 5 DB1 6 DB0 ERAMHI ERAMLO 11 ERAM 12 RWN EXM 15 ...
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February 1997 3 Pin Information (continued DDA V SSA SPARE PACKAGE BALLS SHOULD BE TIED TO "SOFT GND" OR "SIG GND" Note: Solder balls viewed thru package. Figure 3. 144-Pin Plastic Ball Grid Array (Top ...
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DSP1628 Digital Signal Processor 3 Pin Information (continued) Functional descriptions of pins 1—100 are found in Section 6, Signal Descriptions. The functionality of CKI and CKI2 pins are mask-programmable (see Section 7, Mask-Programmable Options). Input levels on all I and ...
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February 1997 3 Pin Information (continued) Functional descriptions of pins 1—100 are found in Section 6, Signal Descriptions. Table 1. Pin Descriptions (continued) PBGA Pin BQFP Pin TQFP Pin H11 71 H12 72 G11 73 G12 74 F11 75 F12 ...
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DSP1628 Digital Signal Processor 4 Hardware Architecture The DSP1628 device is a 16-bit, fixed-point program- mable digital signal processor (DSP). The DSP1628 consists of a DSP1600 core together with on-chip mem- ory and peripherals. Added architectural features give the DSP1628 ...
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February 1997 4 Hardware Architecture Bit Manipulation Unit (BMU) The BMU extends the DSP1600 core instruction set to provide more efficient bit operations on accumulators. The BMU contains logic for barrel shifting, normaliza- tion, and bit field insertion/extraction. The unit ...
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DSP1628 Digital Signal Processor 4 Hardware Architecture DB[15:0] AB[15:0] ioc ROM 48K x 16 DUAL-PORT RAM [16/8:5,3:1] † 15/ CKI CKI2 CKO RSTB STOP TRAP INT[1:0] IACK VEC[3:0] OR IOBIT[7:4] DO2 OR PSTAT OLD2 OR PODS OCK2 OR ...
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February 1997 4 Hardware Architecture Table 2. DSP1628 Block Diagram Legend Symbol aa<0—1> Alternate Accumulators. ar<0—3> Auxiliary BMU Registers. BIO Bit Input/Output Unit. BMU Bit Manipulation Unit. BREAKPOINT Four Instruction Breakpoint Registers. BYPASS JTAG Bypass Register. cbit Control Register for ...
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DSP1628 Digital Signal Processor 4 Hardware Architecture Parallel Host Interface (PHIF) The PHIF is a passive, 8-bit parallel port which can in- terface to an 8-bit bus containing other Lucent Technol- ogies DSPs (e.g., DSP1620, DSP1627, DSP1628, DSP1629, DSP1611, DSP1616, ...
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February 1997 4 Hardware Architecture Data Arithmetic Unit (DAU) The data arithmetic unit (DAU) contains 16-bit parallel multiplier that generates a full 32-bit product in one instruction cycle. The product can be accumulated with one of two ...
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DSP1628 Digital Signal Processor 4 Hardware Architecture CONTROL ins (16) inc (16) x (16) yh (16) yl (16 MPY 32 p (32) SHIFT (– MUX 36 ALU/SHIFT a0 (36) a1 (36) 16 EXTRACT/SAT 14 ...
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February 1997 4 Hardware Architecture Table 3. DSP1600 Core Block Diagram Legend Symbol MPY 16-bit x 16-bit Multiplier. a0—a1 Accumulators 0 and 1 (16-bit halves specified as a0, a0l, a1, and a1l)*. alf AWAIT, LOWPR, Flags. ALU/SHIFT ...
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DSP1628 Digital Signal Processor 4 Hardware Architecture Interruptibility Vectored interrupts are serviced only after the execution of an interruptible instruction. If more than one vectored interrupt is asserted at the same time, the in- terrupts are serviced sequentially according to ...
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February 1997 4 Hardware Architecture Table 4. Interrupt Vector Table Source Vector No Interrupt — Software Interrupt 0x2 INT0 0x1 JINT 0x42 INT1 0x4 TIME 0x10 IBF2 0x14 OBE2 0x18 Reserved 0x1c EREADY 0x20 EOVF 0x24 IBF 0x2c OBE 0x30 ...
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DSP1628 Digital Signal Processor 4 Hardware Architecture The AWAIT bit should be set from within the cache if the code which is executing resides in external ROM where more than one wait-state has been programmed. This ensures that an interrupt ...
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February 1997 4 Hardware Architecture Table 5. Instruction/Coefficient Memory Maps DSP1628x16 X Address AB[0:15] 0 0x0000 4K 0x1000 8K 0x2000 12K 0x3000 16K 0x4000 20K 0x5000 24K 0x6000 28K 0x7000 32K 0x8000 36K 0x9000 40K 0xA000 44K 0xB000 48K 0xC000 ...
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DSP1628 Digital Signal Processor 4 Hardware Architecture Table 6. Data Memory Maps 1628x16 Data Memory Map (Not to Scale) Decimal Address in Address r0, r1, r2 0x0000 16K 0x4000 16,640 0x4100 32K 0x8000 64K – 1 0xFFFF On ...
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February 1997 4 Hardware Architecture 4.5 External Memory Interface (EMI) The external memory interface supports read/write op- erations from instruction/coefficient memory, data memory, and memory-mapped I/O devices. The DSP1628 provides a 16-bit external address bus, AB[15:0], and a 16-bit external ...
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DSP1628 Digital Signal Processor 4 Hardware Architecture 4.6 Bit Manipulation Unit (BMU) The BMU interfaces directly to the main accumulators in the DAU providing the following features: Barrel shifting—logical and arithmetic, left and right shift Normalization and extraction of exponent ...
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February 1997 4 Hardware Architecture While ILD1 and OLD1 are not required externally for multiprocessor operation, they are used internally in the DSP's SIO. Setting the LD field of the master's sioc reg- ister to a logic level 1 will ...
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DSP1628 Digital Signal Processor 4 Hardware Architecture DSP 0 DATA CHANNEL CLOCK ADDRESS/PROTOCOL CHANNEL SYNC SIGNAL Figure 6. Multiprocessor Communication and Connections 4.8 Parallel Host Interface (PHIF) The DSP1628 has an 8-bit parallel host interface for rapid transfer of data ...
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February 1997 4 Hardware Architecture Finally, the assertion level of the output pins, PIBF and POBE, is controlled through bit 4, PFLAG. When PFLAG is set low, PIBF and POBE output pins have positive assertion levels. By setting bit 5, ...
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DSP1628 Digital Signal Processor 4 Hardware Architecture 4.10 Timer The interrupt timer is composed of the timerc (control) register, the timer0 register, the prescaler, and the counter itself. The timer control register (see Table 35, timerc Register) sets up the ...
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February 1997 4 Hardware Architecture In wideband low data rate applications, additive white Gaussian noise (AWGN) is the principle channel impair- ment, and Euclidean branch metric computation for convolutional decoding is selected by resetting the branch metric select bit to ...
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DSP1628 Digital Signal Processor 4 Hardware Architecture Generating polynomials, G(0 G(5 six-delays corresponding to a constraint length of seven, may take part in computing the estimated received signals, E(0, k ...
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February 1997 4 Hardware Architecture DSP Decoding Operation Sequence The DSP operation sequence for invoking the ECCP for an MLSE equalization or convolutional decoding operation is explained with the operation flow diagram in Figure 7. EBUSY = FALSE ECCP OFF ...
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DSP1628 Digital Signal Processor 4 Hardware Architecture Operation of the ECCP To operate the ECCP, the user first programs its mode of operation by setting the control register, ECON, the tra- ceback length register, TBLR, and appropriately initializing the present ...
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February 1997 4 Hardware Architecture Software Architecture The ECCP registers are grouped into two categories: the R-field registers and the internal memory-mapped registers. R-Field Registers: Three registers (ear, edr, and eir) are defined in the core instruction set as programmable ...
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DSP1628 Digital Signal Processor 4 Hardware Architecture ECCP Internal Memory-Mapped Registers: Internal memory-mapped registers are defined in the ECCP address space for control and status purposes and to hold data. A summary of the contents of these registers is given ...
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February 1997 4 Hardware Architecture Table 13. Memory-Mapped Registers (continued) Address Register 0x407 Received Symbol/Channel Tap Register S1H1 0x408 Received Symbol/Channel Tap Register S0H0 0x409 Decoded Symbol Register DSR 0x40a Received Real Signal/Generating Polynomial ZIG10 0x40b Received Imaginary Signal/Generating Polynomial ...
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DSP1628 Digital Signal Processor 4 Hardware Architecture 4.12 JTAG Test Port The DSP1628 uses a JTAG/ IEEE 1149.1 standard five- wire test port (TDI, TDO, TCK, TMS, TRST) for self-test and hardware emulation. An instruction register, a boundary-scan register, a ...
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February 1997 4 Hardware Architecture Table 15. JTAG Boundary-Scan Register Note: The direction of shifting is from TDI to cell 104 to cell 103 . . . to cell 0 of TDO. Cell Type Signal Name/Function 0 OE Controls cells ...
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DSP1628 Digital Signal Processor 4 Hardware Architecture 4.13 Clock Synthesis CKI INPUT CLOCK f CKI PHASE N DETECTOR Nbits[2:0] PLL/SYNTHESIZER The DSP1628 provides an on-chip, programmable clock synthesizer. Figure 10 is the clock source dia- gram. The 1X CKI input ...
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February 1997 4 Hardware Architecture The frequency of the PLL output clock, f mined by the values loaded into the 3-bit N divider and the 5-bit M divider. When the PLL is selected and locked, the frequency of the internal ...
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DSP1628 Digital Signal Processor 4 Hardware Architecture PLL Programming Examples The following section of code illustrates how the PLL would be initialized on powerup, assuming the following oper- ating conditions: CKI input frequency = 10 MHz Internal clock and CKO ...
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February 1997 4 Hardware Architecture 4.14 Power Management There are three different control mechanisms for putting the DSP1628 into low-power modes: the powerc con- trol register, the STOP pin, and the AWAIT bit in the alf register. The PLL can ...
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DSP1628 Digital Signal Processor 4 Hardware Architecture XTLOFF OFF CKI2 SMALL SIGNAL CLOCK MASK-PROGRAMMABLE CKI OPTION CMOS INPUT CLOCK STOP HW STOP SW STOP NOCK CLEAR NOCK RSTB INT0 INT0EN INT1 INT1EN Notes: The functions in the shaded ovals are ...
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February 1997 4 Hardware Architecture Await Bit of the alf Register Setting the AWAIT bit of the alf register causes the processor to go into the standard sleep state or power-saving standby mode. Operation of the AWAIT bit is the ...
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DSP1628 Digital Signal Processor 4 Hardware Architecture Power Management Examples Without the PLL The following examples show the more significant options for reducing the power dissipation. These are valid only if the pllc register is set to disable and deselect ...
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February 1997 4 Hardware Architecture Software Stop. In this case, all internal clocking is disabled. INT0, INT1, or RSTB may be used to reenable the clocks. The power management must be done in correct sequence. powerc = 0x4000 /* SLOWCKI ...
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DSP1628 Digital Signal Processor 4 Hardware Architecture Power Management Examples with the PLL The following examples show the more significant options for reducing power dissipation if operation with the PLL clock synthesizer is desired. Standard Sleep Mode, PLL Running. This ...
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February 1997 4 Hardware Architecture Sleep with Slow Internal Clock and Small-Signal Disabled, PLL Disabled. If the target device contains the small- signal clock option, the clock input circuitry can be powered down to further reduce power. In this case, ...
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DSP1628 Digital Signal Processor 5 Software Architecture 5.1 Instruction Set The DSP1628 processor has seven types of instruc- tions: multiply/ALU, special function, control, F3 ALU, BMU, cache, and data move. The multiply/ALU instruc- tions are the primary instructions used to ...
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February 1997 5 Software Architecture A single-cycle squaring function is provided in DSP1628. By setting the bit in the auc register, any instruction that loads the high half of the y register also loads the x ...
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DSP1628 Digital Signal Processor 5 Software Architecture Special Function Instructions All forms of the special function require one word of program memory and execute in one instruction cycle. (If PC points to external memory, add programmed wait-states ...
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February 1997 5 Software Architecture Control Instructions All control instructions executed unconditionally execute in two cycles, except icall which takes three cycles. Control instructions executed conditionally execute in three instruction cycles. (If PC, pt point to external memory, ...
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DSP1628 Digital Signal Processor 5 Software Architecture Conditional Mnemonics (Flags) Table 21 lists mnemonics used in conditional execution of special function and control instructions. Table 21. DSP1628 Conditional Mnemonics Test Meaning pl Result is nonnegative (sign bit is bit 35). ...
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February 1997 5 Software Architecture F3 ALU Instructions These instructions are implemented in the DSP1600 core. They allow accumulator two-operand operations with ei- ther another accumulator, the p register 16-bit immediate operand (IM16). The result is placed in ...
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DSP1628 Digital Signal Processor 5 Software Architecture Barrel Shifter >> IM16 Arithmetic right shift by immediate (36-bit, sign filled in); 2-cycle, 2-word >> arM Arithmetic right shift by arM (36-bit, sign filled in); 1-cycle. ...
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February 1997 5 Software Architecture Cache Instructions Cache instructions require one word of program memory. The do instruction executes in one instruction cycle, and the redo instruction executes in two instruction cycles. (If PC points to external memory, add programmed ...
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DSP1628 Digital Signal Processor 5 Software Architecture Data Move Instructions Data move instructions normally execute in two instruction cycles. ( point to external memory, any pro- grammed wait-states must be added. In addition and rM ...
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February 1997 5 Software Architecture 5.2 Register Settings Tables 26 through 42 describe the programmable registers of the DSP1628 device. Table 44 describes the register settings after reset. Note that the following abbreviations are used in the tables ...
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DSP1628 Digital Signal Processor 5 Software Architecture Table 27. Time-Division Multiplex Slot Registers tdms Bit 9 8 Field SYNCSP MODE Field Value † ‡ SYNCSP 0 1 MODE 0 1 1xxxxxx TRANSMIT SLOT x1xxxxx xx1xxxx xxx1xxx xxxx1xx xxxxx1x xxxxxx1 SYNC ...
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February 1997 5 Software Architecture Table 28. Serial Receive/Transmit Address Registers srta Bit Field RECEIVE ADDRESS Field RECEIVE ADDRESS 1xxxxxxx x1xxxxxx xx1xxxxx xxx1xxxx xxxx1xxx xxxxx1xx xxxxxx1x xxxxxxx1 TRANSMIT ADDRESS 1xxxxxxx x1xxxxxx xx1xxxxx xxx1xxxx xxxx1xxx xxxxx1xx ...
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DSP1628 Digital Signal Processor 5 Software Architecture Table 30. Processor Status Word (psw) Register Bit Field DAU FLAGS Field Value DAU FLAGS* Wxxx xWxx xxWx xxxW a1[V] W a1[35:32] Wxxx xWxx xxWx xxxW a0[V] W a0[35:32] ...
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February 1997 5 Software Architecture Table 32. Parallel Host Interface Control (phifc) Register Bit 15—7 6 Field Reserved PSOBEF Field Value PMODE 0 1 PSTROBE 0 1 PSTRB 0 1 PBSELF 0 1 PFLAG 0 1 PFLAGSEL 0 1 PSOBEF ...
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DSP1628 Digital Signal Processor 5 Software Architecture Table 35. timerc Register Bit 15—7 Field Reserved DISABLE Field Value DISABLE 0 Timer enabled. 1 Timer and prescaler disabled. The period register and timer0 are not reset. RELOAD 0 Timer stops after ...
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February 1997 5 Software Architecture Table 37. sbit Register Bit Field DIREC[7:0] Field Value DIREC 1xxxxxxx IOBIT7 is an output (input when 0). x1xxxxxx IOBIT6 is an output (input when 0). xx1xxxxx IOBIT5 is an ...
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DSP1628 Digital Signal Processor 5 Software Architecture Table 39. alf Register Bit 15 14 Field AWAIT LOWPR Field Value AWAIT 1 0 LOWPR 1 0 FLAGS — Bit Flag 13—9 Reserved 8 ebusy* ECCP BUSY 7 nmns1 NOT-MINUS-ONE from BMU ...
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February 1997 5 Software Architecture Table 42. ioc Register* Bit Field Reserved EXTROM CKO2 EBIOH * The field definitions for the ioc register are different from the DSP1610. ioc Fields ioc Field EXTROM If 1, sets AB15 ...
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DSP1628 Digital Signal Processor 5 Software Architecture Table 43. powerc Register The powerc register configures various power management modes. Bit Field XTLOFF SLOWCKI NOCK INT0EN rsrvd Note: The reserved (rsrvd) bits should always be written with zeros ...
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February 1997 5 Software Architecture Table 44. Register Settings After Reset A • indicates that this bit is unknown on powerup reset and unaffected on subsequent reset indicates that this bit shadows the PC. P indicates the value ...
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DSP1628 Digital Signal Processor 5 Software Architecture 5.3 Instruction Set Formats This section defines the hardware-level encoding of the DSP1628 device instructions. Multiply/ALU Instructions Format 1: Multiply/ALU Read/Write Group Field T Bit Format 1a: Multiply/ALU Read/Write ...
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February 1997 5 Software Architecture Control Instructions Format 4: Branch Direct Group Field T Bit Format 5: Branch Indirect Group Field T Bit Format 6: Conditional Branch Qualifier/Software Interrupt (icall) Note that ...
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DSP1628 Digital Signal Processor 5 Software Architecture Field Descriptions Table 45. T Field Specifies the type of instruction. T Operation 0000x goto JA 00010 Short imm j, k, rb, re 00011 Short imm r0, r1, r2, r3 00100 Y = ...
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February 1997 5 Software Architecture Table 51. Y Field Specifies the form of register indirect addressing with postmodification. Y Operation * r0 0000 * r0++ 0001 * r0-- 0010 * r0++j 0011 * r1 0100 * r1++ 0101 * r1-- ...
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DSP1628 Digital Signal Processor 5 Software Architecture Table 55. R Field Specifies the register for data move instructions. R Register R 000000 r0 100000 000001 r1 100001 000010 r2 100010 000011 r3 100011 000100 j 100100 000101 k 100101 000110 ...
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February 1997 5 Software Architecture N Field Number of instructions to be loaded into the cache. Zero implies redo operation. K Field Number of times the N instructions in cache are to be executed. Zero specifies use of value in ...
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DSP1628 Digital Signal Processor 6 Signal Descriptions AB[15:0] DB[15:0] RWN EXTERNAL EXM MEMORY INTERFACE EROM ERAMHI IO ERAMLO DSEL DO1 OLD1 OCK1 OBE1 SERIAL DI1 INTERFACE #1 ILD1 ICK1 IBF1 SYNC1 SADD1 DOEN1 Figure 12 shows the pinout for the ...
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February 1997 6 Signal Descriptions (continued) CKI2 Input Clock 2: Used with mask-programmable input clock options which require an external small signal dif- ferential across CKI and CKI2 (see Table 1, Pin De- scriptions). When the CMOS option is selected, ...
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DSP1628 Digital Signal Processor 6 Signal Descriptions (continued) 6.2 External Memory Interface The external memory interface is used to interface the DSP1628 to external memory and I/O devices. It sup- ports read/write operations from/to program and data memory spaces. The ...
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February 1997 6 Signal Descriptions (continued) 6.3 Serial Interface #1 The serial interface pins implement a full-featured syn- chronous/asynchronous serial I/O channel. In addition, several pins offer a glueless TDM interface for multipro- cessing communication applications (see Figure 6, Mul- ...
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DSP1628 Digital Signal Processor 6 Signal Descriptions (continued) 6.4 Parallel Host Interface or Serial Interface #2 and Control I/O Interface This interface pin multiplexes a parallel host interface with a second serial I/O interface and a 4-bit I/O inter- face. ...
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February 1997 6 Signal Descriptions (continued) 6.6 JTAG Test Interface The JTAG test interface has features that allow pro- grams and data to be downloaded into the DSP via four pins. This provides extensive test and diagnostic capa- bility. In ...
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DSP1628 Digital Signal Processor 7 Mask-Programmable Options The DSP1628 contains a ROM that is mask-programmable. The selection of several programmable features is made when a custom ROM is encoded. These features select the input clock options, the instruction/coefficient memory map ...
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February 1997 8 Device Characteristics 8.1 Absolute Maximum Ratings Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are abso- lute stress ratings only. Functional operation of the device is not implied at ...
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DSP1628 Digital Signal Processor 8 Device Characteristics 8.4 Package Thermal Considerations The recommended operating temperature specified above is based on the maximum power, package type, and maximum junction temperature. The following equations describe the relationship between these parameters. If the ...
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DSP1628 Digital Signal Processor 9 Electrical Characteristics and Requirements The following electrical characteristics are preliminary and are subject to change. Electrical characteristics refer to the behavior of the device under specified conditions. Electrical requirements refer to conditions imposed on the ...
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February 1997 9 Electrical Characteristics and Requirements Table 63. PLL Electrical Specifications, VCO Frequency Ranges Parameter VCO frequency range ( 10%) DD Input Jitter at CKI Table 64. PLL Electrical Specifications and pllc Register Settings pllc13 M ...
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DSP1628 Digital Signal Processor 9 Electrical Characteristics and Requirements – 0 – 0 – 0 – 0 Figure 9. Plot of V 0.4 0.3 0.2 0.1 ...
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February 1997 9 Electrical Characteristics and Requirements 9.1 Power Dissipation Power dissipation is highly dependent on DSP program activity and the frequency of operation. The typical power dissipation listed is for a selected application. The following electrical characteristics are preliminary ...
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DSP1628 Digital Signal Processor 9 Electrical Characteristics and Requirements Table 65. Power Dissipation and Wake-Up Latency (continued) Operating Mode (Unused inputs SS) V DD= I/O Units ON, ECCP OFF Sleep with Slow Internal Clock Small ...
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February 1997 10 Timing Characteristics for 2.7 V Operation The following timing characteristics and requirements are preliminary information and are subject to change. Timing characteristics refer to the behavior of the device under specified conditions. Timing requirements refer to conditions ...
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DSP1628 Digital Signal Processor 10 Timing Characteristics for 2.7 V Operation 10.1 DSP Clock Generation CKI † CKO ‡ CKO See Table 62 for input ...
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February 1997 10 Timing Characteristics for 2.7 V Operation 10.2 Reset Circuit The DSP1628 has two external reset pins: RSTB and TRST. At initial powerup the supply voltage falls below V MIN* and a device reset is required, ...
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DSP1628 Digital Signal Processor 10 Timing Characteristics for 2.7 V Operation 10.3 Reset Synchronization V IH CKI RSTB CKO CKO See Table 62 ...
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February 1997 10 Timing Characteristics for 2.7 V Operation 10.4 JTAG I/O Specifications t155 V IH TCK V IL t15 V IH TMS V IL t17 V IH TDI TDO V OL Table 71. Timing Requirements ...
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DSP1628 Digital Signal Processor 10 Timing Characteristics for 2.7 V Operation 10.5 Interrupt V OH CKO t21 V IH INT[1: t22 V OH IACK † VEC[3: CKO is free-running. ...
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February 1997 10 Timing Characteristics for 2.7 V Operation 10.6 Bit Input/Output (BIO CKO V OL IOBIT V OH (OUTPUT IOBIT IH (INPUT Figure 16. Write Outputs Followed by Read Inputs (cbit = ...
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DSP1628 Digital Signal Processor 10 Timing Characteristics for 2.7 V Operation 10.7 External Memory Interface The following timing diagrams, characteristics, and requirements do not apply to interactions with delayed external memory enables unless so stated. See the DSP1611/17/18/27 Digital Signal ...
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February 1997 10 Timing Characteristics for 2.7 V Operation V OH CKO ENABLE t128 number of wait-states. Figure 19. External Memory ...
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DSP1628 Digital Signal Processor 10 Timing Characteristics for 2.7 V Operation (MWAIT = 0x1002 CKO ERAMLO EROM V OL t133 V OH RWN V OL ...
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February 1997 10 Timing Characteristics for 2.7 V Operation (MWAIT = 0x1002 CKO ERAMLO EROM RWN ...
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DSP1628 Digital Signal Processor 10 Timing Characteristics for 2.7 V Operation 10.8 PHIF Specifications For the PHIF, read means read by the external user (output by the DSP); write is similarly defined. The 8-bit reads/ writes are identical to one-half ...
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February 1997 10 Timing Characteristics for 2.7 V Operation 16-bit READ V IH PCSN V IL t55 V IH PODS V IL t56 V IH PIDS PBSEL V OL t53 V OH POBE ...
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DSP1628 Digital Signal Processor 10 Timing Characteristics for 2.7 V Operation 16-bit READ V IH PCSN PDS V IL t41 V IH PRWN V IL t43 V IH PBSEL V IL t45 V IH PSTAT V ...
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February 1997 10 Timing Characteristics for 2.7 V Operation 16-bit READ V IH PCSN V IL t55 V IH PODS V IL t56 V IH PIDS PBSEL V OL t53 V OH POBE ...
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DSP1628 Digital Signal Processor 10 Timing Characteristics for 2.7 V Operation V IH PCSN PODS(PDS PIDS(PRWN PBSEL PSTAT [7:0] ...
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February 1997 10 Timing Characteristics for 2.7 V Operation V – IH RSTB V – – OH POBE V – – OH PIBF V – OL Figure 27. PHIF, PIBF, and POBE Reset Timing Diagram Table ...
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DSP1628 Digital Signal Processor 10 Timing Characteristics for 2.7 V Operation 10.9 Serial I/O Specifications t72 V – IH ICK V – IL t75 t73 V – IH ILD V – – – ...
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February 1997 10 Timing Characteristics for 2.7 V Operation V – OH ICK V – OL t101 t76a V – OH ILD V – – – – OH IBF V – ...
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DSP1628 Digital Signal Processor 10 Timing Characteristics for 2.7 V Operation t82 V – IH OCK V – IL t85 t83 V – IH OLD V – IL t88 V – OH DO* V – OL t94 V – OH ...
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February 1997 10 Timing Characteristics for 2.7 V Operation V – OH OCK V – OL t102 t86a V – OH OLD V – OL t88 V – – OL t94 V – OH SADD V – ...
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DSP1628 Digital Signal Processor 10 Timing Characteristics for 2.7 V Operation V – OH CKO V – OL t97 V – OH ICK V – OL t99 V – OH OCK V – – OH ICK/OCK* V – ...
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February 1997 10 Timing Characteristics for 2.7 V Operation 10.10 Multiprocessor Communication OCK/ICK t113 t112 V – IH SYNC V – – OH DO/D1 B15 V – OL SADD V – OH DOEN V – Negative ...
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DSP1628 Digital Signal Processor 11 Outline Diagrams 11.1 100-Pin BQFP (Bumpered Quad Flat Pack) All dimensions are in millimeters EDGE CHAMFER 38 39 DETAIL A 0.635 TYP GAGE PLANE SEATING PLANE 109 22.860 0.305 22.350 0.255 19.050 0.405 ...
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February 1997 11 Outline Diagrams (continued) 11.2 100-Pin TQFP (Thin Quad Flat Pack) All dimensions are in millimeters. PIN #1 IDENTIFIER ZONE 100 DETAIL A 0.50 TYP GAGE PLANE SEATING PLANE Lucent Technologies Inc. 16.00 0.20 14.00 ...
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DSP1628 Digital Signal Processor 11 Outline Diagrams (continued) 11.3 144-Pin PBGA (Plastic Ball Grid Array) All dimensions are in millimeters. PIN A1 CORNER TOP VIEW MOLD COMPOUND PWB 0.36 SIDE VIEW 0.40 BOTTOM VIEW PIN A1 CORNER 111 13.00 0.20 ...
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For additional information, contact your Microelectronics Group Account Manager or the following: INTERNET: http://www.lucent.com/micro U.S.A.: Microelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18103 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106), e-mail docmaster@micro.lucent.com ASIA PACIFIC: ...