ds96-039wdsp ETC-unknow, ds96-039wdsp Datasheet - Page 47

• Manufacturer Part Number: ds96-039wdsp
• Description: Clarification Serial Control Register Description Dsp1620/27/28/29 Devices
• Manufacturer: ETC-unknow

February 1997
4 Hardware Architecture
Sleep with Slow Internal Clock and Small-Signal Disabled, PLL Disabled. If the target device contains the small-
signal clock option, the clock input circuitry can be powered down to further reduce power. In this case, the slow
clock must be selected first, and then the PLL must be disabled, since the PLL cannot run without the clock input
circuitry being active.
sleep:a0 = 0x8000
cont: powerc = 0x00F0
Software Stop, PLL Disabled. In this case, all internal clocking is disabled. INT0, INT1, or RSTB may be used to
reenable the clocks. The power management must be done in the correct sequence, with the PLL being disabled
before shutting down the clock input buffer.
sopor:powerc = 0xF000
cont: powerc = 0x4000
Lucent Technologies Inc.
powerc = 0x40F0
2*nop
pllc = 0x29F2
powerc = 0xC0F0
do 1 {
alf = a0
nop
}
nop
nop
powerc = 0x40F0
call xtlwait
pllc = 0xE9F2
call pllwait
2*nop
powerc = 0x0000
powerc = 0x4000
2*nop
pllc = 0x29F2
powerc = 0xD000
3*nop
call xtlwait
pllc = 0xE9F2
call pllwait
powerc = 0x0
2*nop
ins = 0x0010
/* Turn off peripherals and select slow clock */
/* Wait for slow clock to take effect */
/* Disable PLL (assume N = 1,M = 20, LF = 1001) */
/* Disable small-signal input buffer */
/* Set alf register in cache loop if running from */
/* external memory with >1 wait state */
/* Stop internal processor clock, interrupt circuits */
/* active */
/* Needed for bedtime execution. Reduced sleep power
/* consumed here.... Interrupt wakes up device */
/* Clear XTLOFF, leave PLL disabled */
/* Wait until small-signal is stable */
/* Enable PLL, continue to run off slow clock */
/* Loop to check for LOCK flag assertion */
/* Select high-speed PLL based clock */
/* Wait for it to take effect */
/* Turn peripherals back on */
/* SLOWCKI asserted */
/* Wait for slow clock to take effect */
/* Disable PLL (assume N = 1, M = 20, LF = 1001) */
/* XTLOFF asserted, if applicable and INT0EN
/* asserted */
/* NOCK asserted, all clocks stop */
/* Minimum switching power consumed here */
/* Some nops will be needed */
/* INT0 pin clears NOCK field, clocking resumes */
/* INTOEN cleared and XTLOFF cleared, if applicable */
/* Wait until small-signal is stable */
/* if applicable */
/* Enable PLL, continue to run off slow clock */
/* Loop to check for LOCK flag assertion */
/* Select high-speed PLL based clock */
/* Wait for it to take effect */
/* Clear the INT0 status bit */
(continued)
DSP1628 Digital Signal Processor
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