ds96-039wdsp ETC-unknow, ds96-039wdsp Datasheet - Page 100

• Manufacturer Part Number: ds96-039wdsp
• Description: Clarification Serial Control Register Description Dsp1620/27/28/29 Devices
• Manufacturer: ETC-unknow

February 1997
10 Timing Characteristics for 2.7 V Operation
Table 86. Timing Requirements for PHIF Intel Mode Signaling
Table 87. Timing Characteristics for PHIF Intel Mode Signaling
* t53 should be referenced to the rising edge of PCSN or PODS, whichever comes first. t54 should be referenced to the rising edge of
† POBE and PIBF may be programmed to be the opposite logic levels shown in the diagram (positive assertion levels shown). t53 and
Lucent Technologies Inc.
PBSEL
PODS
PCSN
POBE
PCSN or PIDS, whichever comes first.
t54 apply to the inverted levels as well as those shown.
PIDS
PIBF
Abbreviated Reference
Abbreviated Reference
V
V
V
V
V
V
V
V
V
V
V
V
OH
OH
OH
OL
OL
OL
IH
IH
IH
IL
IL
IL
t53*
t54*
16-bit READ
t55
t56
Figure 23. PHIF Intel Mode Signaling (Pulse Period and Flags) Timing Diagram
t55
t53
t56
PCSN/PODS/PIDS Pulse Width (high to low)
PCSN/PODS/PIDS Pulse Width (low to high)
PCSN/PODS to POBE
PCSN/PIDS to PIBF
16-bit WRITE
t55
t55
t54
t56
t56
Parameter
Parameter
†
(high to high)
†
(high to high)
(continued)
8-bit READ
DSP1628 Digital Signal Processor
t53
t56
Min
20.5
20.5
—
—
Min
t55
Max
8-bit WRITE
Max
17
17
—
—
t54
t56
Unit
Unit
ns
ns
ns
ns
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