ds96-039wdsp ETC-unknow, ds96-039wdsp Datasheet - Page 8

• Manufacturer Part Number: ds96-039wdsp
• Description: Clarification Serial Control Register Description Dsp1620/27/28/29 Devices
• Manufacturer: ETC-unknow

DSP1628 Digital Signal Processor
3 Pin Information
Functional descriptions of pins 1—100 are found in Section 6, Signal Descriptions. The functionality of CKI and CKI2
pins are mask-programmable (see Section 7, Mask-Programmable Options). Input levels on all I and I/O type pins
are designed to remain at full CMOS levels when not driven by the DSP.
Table 1. Pin Descriptions
*
† 3-states when RSTB = 0 and INT0 = 1. Output = 1 when RSTB = 0 and INT0 = 0, except CKO which is free-running.
‡ Pull-up devices on input.
§ 3-states by JTAG control.
** See Section 7, Mask-Programmable Options.
†† For SIO multiprocessor applications, add 5 k external pull-up resistors to SADD1 and/or SADD2 for proper initialization.
6
M1, K3, M2,
C2, C1, C3,
G2, H1, H2,
PBGA Pin
B6, A6, B5,
A5, B4, A4,
B3, A3, B2,
A2, A1, B1,
L3, M3, L4,
K2, L1, L2,
J1, J2, K1,
3-states when RSTB = 0, or by JTAG control.
M11
K10
K11
K12
L10
L11
L12
J11
J12
M4
M5
M6
M7
M8
M9
D1
D2
E1
E2
G1
F1
F2
L5
L6
L7
L8
L9
BQFP Pin TQFP Pin
10, 11, 12,
15, 16, 17,
28, 29, 31,
32, 33, 34,
35, 36, 37,
40, 41, 42,
43, 44, 45,
1, 2, 3, 4,
5, 7, 8, 9,
18, 19
20
21
23
24
25
27
46
47
48
50
51
52
53
54
56
57
58
59
61
62
65
66
67
68
69
70
(continued)
88, 89, 90,
91, 92, 94,
95, 96, 97,
15, 16, 18,
19, 20, 21,
22, 23, 24,
27, 28, 29,
30, 31, 32,
98, 99, 2,
3, 4, 5, 6
10
11
12
14
33
34
35
37
38
39
40
41
43
44
45
46
48
49
52
53
54
55
56
57
7
8
VEC0/IOBIT7
VEC1/IOBIT6
VEC2/IOBIT5
VEC3/IOBIT4
IOBIT3/PB7
IOBIT2/PB6
ERAMLO
DB[15:0]
ERAMHI
Symbol
AB[15:0]
EROM
CKI2**
STOP
TRAP
RSTB
RWN
CKI**
IACK
EXM
INT1
INT0
CKO
TMS
TDO
TCK
TDI
IO
Type
I/O*
I/O*
I/O*
I/O*
I/O*
I/O*
I/O*
I/O*
O
O
O
O
O
O*
O*
O
O
I
I
I
I
I
I
I
I
‡
‡
I
I
†
†
†
†
†
†
§
Status/Control Bit 2/PHIF Data Bus Bit 6.
External Memory Data Bus 15—0.
Data Address 0x4000 to 0x40FF I/O Enable.
Data Address 0x8000 to 0xFFFF External RAM
Enable.
Data Address 0x4100 to 0x7FFF External RAM
Enable.
Program Address External ROM Enable.
Read/Write Not.
External ROM Enable.
External Memory Address Bus 15—0.
Vectored Interrupt 1.
Vectored Interrupt 0.
Interrupt Acknowledge.
STOP Input Clock.
Nonmaskable Program Trap/Breakpoint Indication.
Reset Bar.
Processor Clock Output.
JTAG Test Clock.
JTAG Test Mode Select.
JTAG Test Data Output.
JTAG Test Data Input.
Vectored Interrupt Indication 0/Status/Control Bit 7.
Vectored Interrupt Indication 1/Status/Control Bit 6.
Vectored Interrupt Indication 2/Status/Control Bit 5.
Vectored Interrupt Indication 3/Status/Control Bit 4.
Status/Control Bit 3/PHIF Data Bus Bit 7.
Mask-Programmable Input Clock Option
CMOS
V
CKI
SSA
Name/Function
Lucent Technologies Inc.
Small Signal
February 1997
VCM
VAC