ds96-039wdsp ETC-unknow, ds96-039wdsp Datasheet - Page 34

• Manufacturer Part Number: ds96-039wdsp
• Description: Clarification Serial Control Register Description Dsp1620/27/28/29 Devices
• Manufacturer: ETC-unknow

4 Hardware Architecture
ECCP Internal Memory-Mapped Registers: Internal memory-mapped registers are defined in the ECCP address space
for control and status purposes and to hold data. A summary of the contents of these registers is given in Table 13.
Table 13. Memory-Mapped Registers
DSP1628 Digital Signal Processor
32
0x0000—0x007F
0x0080—0x01FF
0x0200—0x027F
0x0280—0x03FF
Address
0x400
0x401
0x402
0x403
0x404
0x405
0x406
Next State Register
NS[0:63]—24-bit words split across two ad-
dress locations
Reserved
Present State Register
PS[0:63]—24-bit words split across two ad-
dress locations
Reserved
Current Symbol Pointer
SYC
Control Register
ECON
Traceback Length Register
TBLR
Received Symbol/Channel Tap Register
S5H5
Received Symbol/Channel Tap Register
S4H4
Received Symbol/Channel Tap Register
S3H3
Received Symbol/Channel Tap Register
S2H2
Register
(continued)
Bit 31:16 is addressed by even address.
Bit 31:24 zero.
Bit 23:16 most significant byte of path cost.
Bit 15: 0 is addressed by odd address.
Bit 15:0 lower 2 bytes of path cost.
Bit 31:16 is addressed by even address.
Bit 31:24 zero.
Bit 23:16 most significant byte of path cost.
Bit 15:0 is addressed by odd address.
Bit 15:0 lower 2 bytes of path cost.
Bit 5:0 is used.
Bit 15:6 reserved.
Bit 0 is soft decision select.
Bit 1 is Manhattan/Euclidean branch metric select.
Bit 2 is soft/hard decision select.
Bit 3 is reserved.
Bit 7:4 is reserved.
Bit 10:8 is code rate select.
Bit 11 is reserved.
Bit 14:12 is constraint length select.
Bit 15 is reserved.
Bit 5:0 is used.
Bit 15:6 is reserved.
Convolutional decoding case:
MLSE equalization case:
Convolutional decoding case:
MLSE equalization case:
Convolutional decoding case:
MLSE equalization case:
Convolutional decoding case:
MLSE equalization case:
Bit 7:0 is reserved.
Bit 15:8 is S5.
Bit 7:0 is HQ5.
Bit 15:8 is HI5.
Bit 7:0 is reserved.
Bit 15:8 is S4.
Bit 7:0 is HQ4.
Bit 15:8 is HI4.
Bit 7:0 is reserved.
Bit 15:8 is S3.
Bit 7:0 is HQ3.
Bit 15:8 is HI3.
Bit 7:0 is reserved.
Bit 15:8 is S2.
Bit 7:0 is HQ2.
Bit 15:8 is HI2.
Register Bit Field
Lucent Technologies Inc.
February 1997